Dhanunjaya Yangala Email & Phone Number

Dhanunjaya | Semiconductor Design Verification EngineerI am a Design Verification Engineer with 3.3 years of industry experience in Subsystem and IP level verification. I have worked on coverage driven and constrained random verification and have developed UVM based testbenches. Currently contributing at Maxlinear to Verifying Central Processing Unit Sub System for CHIRON_V1 RPHY Device on SOC level. My previous roles at Qualcomm as a client involved DDR Subsystem Firmware (DSF) on subsystem level verification, and at Frenustech, I worked on IP verification and C-based test cases for APB protocol and SHA algorithm. My skills include UVM, SV, Verilog, C, and proficiency in protocols such as I2C, SPI, AHB, and APB. Familiar with Gvim and Linux environments.Experience:->Maxlinear (Current Position):Working on Verification of Central Processing Unit Sub System for CHIRON_V1 RPHY DeviceResponsibilities :