Dhara Devani Email & Phone Number

Ahmedabad, Gujarat, India

Handled multiple blocks of 5nM/7nM for different customers:Main responsibility includes:- Understanding the block size, instance count, synthesis timing, etc- Responsible for floor-planning, timing constraints, clock tree optimization, routing, extraction and timing closure-Execute block level place and route assignments- Close STA timing across all corners and modes for blocks- Work with design teams for closing CTS, IO timing, DFT timing.

Ahmedabad Area, India

Deep understanding of all stages of ASIC Physical implementation including Floor planning, Power planning, Placement, CTS and Routing.My responsibilities are:- Creating and developing EDA tools similar to Tweaker. Primarily responsible for Max Transition.- Learn the basics of Prime Time (PT) tool. Timing Analysis/Closure using Primetime- Learn the basics of ICC tool.- Learn the basics of P&R flow and its implementation.- Script development using TCL

Ahmedabad Area, India

Successfully completed ASIC physical design training provided by Einfochips Training & Research Academy (EITRA).This training enables me to clear all basic concepts required to be an Asic Physical Design engineer. These concepts are : Linux, Pearl, Verilog, TCL, ICC tool, PNR flow, etc.