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Dharmendra Patel Email & Phone Number
Founding Member and Director(Design Verification)
at
Upscale ai
2 work emails found
@paloaltonetworks.com
2 phones found area 408
LinkedIn matched
✓ Verified August 2026
4 data sources
Profile completeness 71%
Current company
Role
Founding Member and Director(Design Verification)
Location
Santa Clara, California, United States
Company size
Who is Dharmendra Patel? Overview
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Quick answer
Dharmendra Patel is listed as Founding Member and Director(Design Verification) at Upscale ai, a with 12 employees, based in Santa Clara, California, United States. AeroLeads shows a work email signal at paloaltonetworks.com, phone signal with area code 408, and a matched LinkedIn profile for Dharmendra Patel.
Dharmendra Patel previously worked as Sr. Principal Engineer - ASIC Verification at Auradine and Sr. Manager - ASIC Verification at Palo Alto Networks.
Company email context
Email format at Upscale ai
This section adds company-level context without repeating Dharmendra Patel's masked contact details.
{first_initial}{last}@paloaltonetworks.com
89% confidence
AeroLeads found 2 current-domain work email signals for Dharmendra Patel. Compare company email patterns before reaching out.
Profile bio
About Dharmendra Patel
Experience in complex ASIC verification including- Architecting and developing verification environment- Developing verification IPs- Creating test plans and Coverage plans and executing them- Enhancing block level verification environment for chip level- Integrating 3rd party verification IPsSpecialties: - Verification languages : System Verilog, e (Specman), Verilog , VHDL- Verification Methodology : UVM, OVM, eRM - Scripting language : Perl- Gate level simulation (including timing (SDF) simulation).- Technology/Protocol experience : Ethernet (400G/100G/40G/10G/1G), PCIE, Interlaken, SPI, AMBA AHB, AMBA APB, AMBA AXI.
Current workplace
Dharmendra Patel's current company
Company context helps verify the profile and gives searchers a useful next step.
Upscale Ai
12 roles
Dharmendra Patel work experience
A career timeline built from the work history available for this profile.
Role listed
Sr. Principal Engineer - Asic Verification
Mar 2021 - May 2023
Sr. Principal Engineer - Asic Verification
Oct 2020 - Mar 2021
Principal Engineer - Asic Verification
Nov 2016 - Oct 2020
Sr. Staff Engineer - Asic Verification
Jun 2014 - Nov 2016
Staff Engineer - Asic Verification
Aug 2012 - Jun 2014
Verification Engineer
Altera
ARM based SoC verification.
Apr 2012 - Aug 2012
Senior Member Of Technical Staff
10GBase-T Ethernet PHY chip verification using specman/system verilog HVLs and eRM/OVM methodologies.
Jul 2006 - Apr 2012
Aug 2003 - May 2006
Lecturer
Nirma University
Lecturer - Electronics and Communication department
Mar 2002 - Aug 2003
FAQ
Frequently asked questions about Dharmendra Patel
Quick answers generated from the profile data available on this page.
What company does Dharmendra Patel work for?
Dharmendra Patel works for Upscale ai.
What is Dharmendra Patel's role at Upscale ai?
Dharmendra Patel is listed as Founding Member and Director(Design Verification) at Upscale ai.
What is Dharmendra Patel's email address?
AeroLeads has found 2 work email signals at @paloaltonetworks.com for Dharmendra Patel at Upscale ai.
What is Dharmendra Patel's phone number?
AeroLeads has found 2 phone signal(s) with area code 408 for Dharmendra Patel at Upscale ai.
Where is Dharmendra Patel based?
Dharmendra Patel is based in Santa Clara, California, United States while working with Upscale ai.
What companies has Dharmendra Patel worked for?
Dharmendra Patel has worked for Upscale Ai, Auradine, Palo Alto Networks, Altera, and Aquantia.
How can I contact Dharmendra Patel?
You can use AeroLeads to view verified contact signals for Dharmendra Patel at Upscale ai, including work email, phone, and LinkedIn data when available.
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