Dharmendra Patel Email and Phone Number
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Experience in complex ASIC verification including- Architecting and developing verification environment- Developing verification IPs- Creating test plans and Coverage plans and executing them- Enhancing block level verification environment for chip level- Integrating 3rd party verification IPsSpecialties: - Verification languages : System Verilog, e (Specman), Verilog , VHDL- Verification Methodology : UVM, OVM, eRM - Scripting language : Perl- Gate level simulation (including timing (SDF) simulation).- Technology/Protocol experience : Ethernet (400G/100G/40G/10G/1G), PCIE, Interlaken, SPI, AMBA AHB, AMBA APB, AMBA AXI.
Upscale Ai
View- Website:
- upscaleai.com
- Employees:
- 12
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Upscale AiSanta Clara, Ca, Us
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Sr. Principal Engineer - Asic VerificationAuradine May 2023 - PresentSanta Clara, California, Us -
Sr. Manager - Asic VerificationPalo Alto Networks Mar 2021 - May 2023Santa Clara, California, UsBuilding ASICs for Next Generation Firewalls. -
Sr. Principal Engineer - Asic VerificationPalo Alto Networks Oct 2020 - Mar 2021Santa Clara, California, Us
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Principal Engineer - Asic VerificationPalo Alto Networks Nov 2016 - Oct 2020Santa Clara, California, Us
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Sr. Staff Engineer - Asic VerificationPalo Alto Networks Jun 2014 - Nov 2016Santa Clara, California, Us
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Staff Engineer - Asic VerificationPalo Alto Networks Aug 2012 - Jun 2014Santa Clara, California, Us
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Verification EngineerAltera Apr 2012 - Aug 2012ARM based SoC verification.
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Senior Member Of Technical StaffAquantia Jul 2006 - Apr 2012San Jose, California, Us10GBase-T Ethernet PHY chip verification using specman/system verilog HVLs and eRM/OVM methodologies. -
Asic EngineerEinfochips Aug 2003 - May 2006San Jose, California, UsASIC engineer (Verification engineer). -
LecturerNirma University Mar 2002 - Aug 2003Lecturer - Electronics and Communication department
Frequently Asked Questions about Dharmendra Patel
What company does Dharmendra Patel work for?
Dharmendra Patel works for Upscale Ai
What is Dharmendra Patel's role at the current company?
Dharmendra Patel's current role is ASIC Design Verification Engineer.
What is Dharmendra Patel's email address?
Dharmendra Patel's email address is dp****@****rks.com
What is Dharmendra Patel's direct phone number?
Dharmendra Patel's direct phone number is +140875*****
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