Dhiraj Mallick

Dhiraj Mallick Email and Phone Number

Chief Operating Officer at Cerebras Systems @ Cerebras Systems
Dhiraj Mallick's Location
Menlo Park, California, United States, United States
About Dhiraj Mallick

I am Chief Operating Officer of Cerebras Systems, a venture backed AI leader. I am excited to be leading world class engineering and operations teams in a quest to do something transformational. Prior to this, I was VP Innovation, Pathfinding and Architecture for Intel's Data Center Group, leading a 300 person global team to develop technologies to give us competitive differentiation in compute platforms, memory and communication fabrics and IO, artificial intelligence, security, workload acceleration for network functions, ML, vision, inference and cloud and edge computing. I brought a customer centric mindset to our product development. I have a strong track record of building teams, innovation, and engineering execution. My career spans a range of technologies across semiconductors, systems and enterprise software engineering, artificial intelligence, data center architecture, and a focus on high performance and workload acceleration products. I have experience in setting strategic direction, building and leading executive teams, cultivating partnerships, effective product strategy and executing product and go-to-market plan to consistently deliver value in Enterprise and Datacenter markets. I have built and led organizations at large enterprises and startups alike. I have experience defining, executing and delivering complex products from ideation to volume. I value relationships, nurturing definitional relationships with customers, and have led business development and customer engagements.

Dhiraj Mallick's Current Company Details
Cerebras Systems

Cerebras Systems

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Chief Operating Officer at Cerebras Systems
Dhiraj Mallick Work Experience Details
  • Cerebras Systems
    Chief Operating Officer
    Cerebras Systems Jun 2018 - Present
    Sunnyvale, California, Us
    Cerebras Systems is a team of pioneering computer architects, computer scientists, deep learning engineers and engineers of all types. We have come together to build a new class of computer system that accelerates artificial intelligence by orders of magnitude beyond the current state of the art. I am proud to be leading this world class engineering and operations team. We’re hiring – come join us!”
  • Global Semiconductor Alliance
    Strategic Advisor To Board Of Directors
    Global Semiconductor Alliance Jan 2020 - Present
    Dallas, Texas, Us
    https://www.gsaglobal.org/gsa-leadership/gsa-advisory-group/
  • Tie Silicon Valley
    Charter Member
    Tie Silicon Valley Feb 2021 - Present
    Palo Alto, California, Us
  • Intel Corporation
    Vice President Of Innovation, Pathfinding And Architecture, Data Center Group
    Intel Corporation Nov 2015 - May 2018
    Santa Clara, California, Us
    Led 300 person product architecture, pathfinding and innovation direct org for $20B data center group. The charter included R&D for compute, network and storage platforms, cloud scale compute, IO and memory technologies, Artificial intelligence, graph and computer vision technology, security and workload performance and acceleration. Responsible for driving the thought leadership, technical vision, and strategy that will deliver next-generation data center architectures, solutions, and innovations.
  • Stanford Angels & Entrepreneurs
    Member
    Stanford Angels & Entrepreneurs Feb 2015 - Jan 2018
    See stanfordaande
  • Arteris
    Member Board Of Directors
    Arteris Jan 2014 - Apr 2016
    Campbell, Ca, Us
  • Amd
    General Manager And Corporate Vice President
    Amd Apr 2012 - Aug 2015
    Santa Clara, California, Us
    Owned end-to-end business including P&L responsibility of 125-person business unit that provides turnkey, hyper-scale, converged fabric infrastructure (server, storage, networking) solutions for Telco, Service Providers, Web 2.0, SaaS and Enterprises implementing Private cloud on OpenStack, scale out applications, bare metal workloads, and Hadoop Big Data workloads. Accelerated business growth by setting transformational vision, building new leadership team, leading market and product strategy pivot to new solutions approach focused on Service Provider, and guiding Sales, Marketing and Engineering execution and operational plans. Achieved best financial performance since inception, increasing revenue by over 200% Y-o-Y in 2014 and securing new design wins with current and new blue chip customers in Service Provider and SaaS verticals. Identified and negotiated strategic supply chain agreements with large global server OEMs and ODMs, lowering COGs by 30%. Launched Go-to-Market initiative with Big Data and OpenStack partner ecosystem, resulting in $1M in net new pipeline per week, every week, in the first quarter of 2015. Transformed the leadership team by selectively releasing and hiring key executives to execute the new vision and deliver business results.
  • Easic
    Advisor
    Easic Mar 2014 - Mar 2015
    Santa Clara, Ca, Us
  • Seamicro Inc.
    Vice President Engineering
    Seamicro Inc. Dec 2009 - Feb 2013
    Sunnyvale, Ca, Us
    I built and led a 70-person Engineering team that pioneered the Micro Server category by developing a server with industry leading density and power efficiency and the 1st fabric-based converged infrastructure product. Responsible for defining, planning and delivering SeaMicro hyper-scale converged infrastructure products. Also led strategic joint development partnerships with 3rd party server and semiconductor companies to license and integrate SeaMicro fabric into their SoC and system designs
  • Metaram Inc.
    Vice President Engineering
    Metaram Inc. May 2006 - May 2009
    San Jose, California, Us
    I was one of the first few employees at this VC based startup. I built and motivated a skilled and diverse, 30-person Engineering team to architect and bring to market the first native memory buffer (LR-DIMM) for server main memory, that has since become a highly adopted industry standard. Launched two generations of products, with 1st time production ready silicon. The IP portfolio and assets were sold to Google.
  • Amd
    Director, Global Cad And Eda
    Amd Oct 2005 - Apr 2006
    Santa Clara, California, Us
    I led a global, 125-person team with a $50M cost center budget to provide in-house CAD software solutions and industry standard tools from EDA partners to enable custom high-performance microprocessor designs in deep submicron technologies. Defined a strategy and operational plan, reorganized leadership team, and delivered Construction, Infrastructure and Analysis tools for AMD processor design teams in 65 and 45nm process technologies
  • Amd
    Engineering Director, Athlon64 Client Product
    Amd Oct 2004 - Oct 2005
    Santa Clara, California, Us
    I led a 4-site, 200-person silicon development team to deliver AMD’s first Opteron low power (25W) multi-core client product, 14 months from concept to production tapeout. I was responsible for driving product definition, execution plans and schedules, technical feasibility / tradeoffs, requirements and product specifications with cross-functional teams from Silicon, Technology, Platforms, Business Unit (mobile, server, desktop), Marketing and Product Engineering
  • Amd
    Sr. Mgr, Soc Engineering
    Amd Aug 2004 - Feb 2005
    Santa Clara, California, Us
    I co-led the company's SoC initiative. I was chartered to drive design productivity, IP reuse, and product time to market improvements. I evangelized reuse, developed an IP reuse roadmap and SoC integration methodology, drove adoption of Design synthesis methodology, and reduced time from 1st tape-out to production release by 20%
  • Amd
    Manager, Opteron/Athlon64 Processor Vlsi Design
    Amd Aug 2001 - Aug 2004
    Santa Clara, California, Us
    I built and led a 60-person VLSI design team with a track record of on-time execution on a family of Opteron/Athlon64 production SKUs. This product line accelerated AMD position from 5% to 24% Server Market share
  • Amd
    Technical Lead, Microprocessors
    Amd Jan 1996 - Aug 2001
    Santa Clara, California, Us
    Led a 6 person team to deliver x86 Instruction Decode module on initial Opteron tapeout from 1999-2001. Prior to that, led 20 person VLSI and Physical design teams to successfully deliver 0.18u K6-III 550MHz tapeout and then led a 12 person engineering team to go from initial tapeout to production
  • Nexgen, Inc
    Mts, Microprocessor Circuit Team
    Nexgen, Inc Jul 1994 - Jan 1996
    Circuit & VLSI design technical roles on Nx586 and K-6 designs

Dhiraj Mallick Skills

Asic Semiconductors Soc Eda Cross Functional Team Leadership Ic Processors Microprocessors Go To Market Strategy Vlsi Start Ups Embedded Systems Management Data Center Strategic Partnerships Cloud Computing Leadership High Performance Computing Product Development Ip Entrepreneurship Engineering Pcb Design Silicon Big Data Project Management Program Management Business Strategy Engineering Management Systems Engineering Strategic Thinking Distributed Systems Artificial Intelligence Strategy Software Development Agile Methodologies Architecture System Architecture Integration Change Management Hardware Architecture Product Management Virtualization Enterprise Software Executive Management Physical Design Business Alliances Semiconductor Industry Hardware Strategic Planning Team Leadership Negotiation Technical Leadership Business Planning Product Strategy Infrastructure Product Launch

Dhiraj Mallick Education Details

  • Stanford University
    Stanford University
    Electrical Engineering
  • Stanford University Graduate School Of Business
    Stanford University Graduate School Of Business
    Stanford Executive Accelerator For Intel
  • University Of Rochester
    University Of Rochester
    Electrical Engineering

Frequently Asked Questions about Dhiraj Mallick

What company does Dhiraj Mallick work for?

Dhiraj Mallick works for Cerebras Systems

What is Dhiraj Mallick's role at the current company?

Dhiraj Mallick's current role is Chief Operating Officer at Cerebras Systems.

What is Dhiraj Mallick's email address?

Dhiraj Mallick's email address is dh****@****ail.com

What is Dhiraj Mallick's direct phone number?

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What schools did Dhiraj Mallick attend?

Dhiraj Mallick attended Stanford University, Stanford University Graduate School Of Business, University Of Rochester.

What skills is Dhiraj Mallick known for?

Dhiraj Mallick has skills like Asic, Semiconductors, Soc, Eda, Cross Functional Team Leadership, Ic, Processors, Microprocessors, Go To Market Strategy, Vlsi, Start Ups, Embedded Systems.

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