Principal Engineer
Current
Sep 2023 - Present
AeroLeads people directory · profile
Dhruv Tripathi Email & Phone Number
Principal Engineer
at
Arm
1 work email found
@intel.com
2 phones found area 512
LinkedIn matched
✓ Verified Jul 2026
4 data sources
Profile completeness 100%
Who is Dhruv Tripathi? Overview
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Quick answer
Dhruv Tripathi is listed as Principal Engineer at Arm, based in Austin, Texas Metropolitan Area, United States. AeroLeads shows a work email signal at intel.com, phone signal with area code 512, and a matched LinkedIn profile for Dhruv Tripathi.
Dhruv Tripathi previously worked as Cloud Software Architect, Technical Lead at Intel Corporation and System Software Architect, Technical Lead at Intel Corporation. Dhruv Tripathi holds Master Of Technology (M.Tech.), Electrical And Electronics Engineering from Indian Institute Of Technology, Delhi.
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Email format at Arm
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{first}.{last}@intel.com
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Profile bio
About Dhruv Tripathi
Experienced software professional with a demonstrated history of working on various computer networking software in the semiconductor industry. Work spanning over generic compute processors, to Network Processors to specialized SoCs to latest IPU/DPUs. Expert in designing and development of Network Data Plane software along with Control Plane software on general processors or on SoCs having multiple hardware accelerators. Deep knowledge of networking protocols to build L2/L3 networks (Ethernet/VxLAN/IPvX), L4 transport (UDP/TCP) and Secure Networks (IPsec). Experience of building last mile wireline (DSLAM) and backhaul for wireless access networks (LTE/5G Base Stations). Hands on experience with virtualization/containerization techniques. Expert at embedded C programming for Linux based networking equipments (Routers/Switches), P4 programming for P4 programmable devices, design & development of processor specific micro-code for specialized SoCs. Experience of working on open source platforms such as DPDK, IPDK, ODP, OVS, etc.. Deep knowledge of computer architecture and leveraging it to build optimum embedded software for multi-core processors. Extensive working experience and knowledge of data structures and algorithms.Decades long experience of building software for different SoCs (SnowRidge, Axxia), with embedded Intel / ARM processors and multiple hardware acceleration components for classification, inline and look-aside encryption/decryption and QoS. Expert at building Data Plane software and leveraging hardware offloads (on Intel IPUs a.k.a SmartNICs) for high data rate and low latency, while also providing interface to customer application for dynamic configurations at high update rates. Experience of building containerized solutions using Docker and Kubernetes.Always hands on, contributing directly while guiding large and geographically distributed team in delivering software to multiple Tier-1 Service Providers. Collaborating closely with hardware teams to define product features and provide use cases. Decades long experience of leading through multiple phases of large software projects -- starting from providing RFI response, requirement discussions and agreement with customer, helping management with planning and feature prioritization, system/component design and implementation, guiding QA team towards system testing, performance optimization and fine tuning, final product delivery and maintenance. Always working in agile mode, aiding in continuous integration & continuous delivery.
Listed skills include Ethernet, Arm, Semiconductors, Firmware, and 10 others.
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Dhruv Tripathi's current company
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7 roles
Dhruv Tripathi work experience
A career timeline built from the work history available for this profile.
Cloud Software Architect, Technical Lead
Architecture, design and development of Kubernetes Networking Offload under IPDK Open-Source project for P4-DPDK and Intel IPU for Data Center environment. Design and creation of P4 based packet processing pipeline and dynamic update of P4 tables from Go based Control Plane Software plug-in. Integration of Go Control Plane Software plug-in with Kubernetes CNI (Calico) and Intel IPU SDK over secure gRPC channel.
May 2022 - Sep 2023
System Software Architect, Technical Lead
* 5G Wireless Access Transport softwareDelivery of wireless access transport software for 5G Radio Base Stations. Providing both data plane and control plane software in C, integrated with DPDK and running on multi-core Intel Atom processor in SNR (Snow Ridge) SoC. Software leverages various hardware accelerators for classification (TCAMs), inline IPsec encryption/decryption and egress QoS (Shaping, Scheduling).
Nov 2014 - May 2022
Principal Engineer
Continuation of ADK IP Transport project in LSI after being acquired by Broadcom Inc. (Avago Technologies, at the time).
May 2014 - Nov 2014
Principal Engineer
* ADK IP TransportDesign and development of software for mobile backhaul transport network, in a multi-mode based station, based upon Axxia SoCs (ACP3xxx & AXM5xxx series). Software included fast path micro code for the hardware accelerators and C based APIs for customer applications. Product had support for Ethernet, IPvX, GTPU, OAM, IPsec, etc. and many customer specific proprietary protocols for backplane connectivity. It was integrated with Linux stack to leverage OS network functions.* ADK Ethernet SwitchingMEF compliant Ethernet switching software for Radio Base Stations, based upon Axxia SoC (ACP 34xx). Product featured standard Ethernet switching as well as advanced features required in Service Provider L2 network. Support for Access, Trunk and Tunnel ports and compliant with various IEEE standards such as Q-in-Q, LAG (Link Aggregation), STP, etc. Product utilized Axxia's flexible pipeline architecture, programmable hardware accelerators for data plane and embedded ARM processor for control plane APIs.* TCP OffloadImplementation and offload of entire TCP protocol on Axxia ACP34xx SoC. The software provides Linux like socket interface in C and micro-code for data plane TCP packet processing. The product supported TCP state machine with all the timers., Delayed ACK, Selective ACK, RTT and RTO measurement, Congestion Control (with Slow-Start), Congestion Avoidance, Fast-Retransmit and Fast-Recovery.
Nov 2008 - May 2014
Sr. Software Engineer
* Sim-Q, CRS-1 Simulation Platform- Lead product definition, building and delivery of Simics / Python based Cisco CRS-1 simulation platform, consisting if simulated Line Cards, Route Processing cards and the Fabric Cards that interconnect the chassis.- Getting Cisco IOS-XR software operational on this platfmulti-rack, multi-chassis platform.* RPM-XF on MGX Platform- RPM-XF (Route Processor Module) support on MGX Platform (Multi-media Gateway Switch).
Feb 2007 - Oct 2008
Technical Leader
* OBXDefined the architecture and lead the design for OBX (Office in a Box) software, targeted towards SMBs (Small and Medium Businesses), based upon Agere's SoC (APP3xx series). Data plane software in Agere's micro code (FPL/CNP), while control plane configuration interface in C. Features supported, such as, L2 switching, L3 routing, VLAN capability, NAT, QoS and ACL based firewall. Role required working with customer for feature definition and working with third party vendor for stack integration.* DSLAMLead architecture definition and system software design for DSLAM using Agere's Soc (APP3xx series). Incorporated rich L2 features such as IPoA, IPoEoA, PPPoA and PPPoEoA along with VLAN, ACL, DiffServ, IGMP, VMAC, STP, Link Aggregation, etc. Role required requirement and features discussion with customer, system design and architecture, implementation and testing of the critical software components.* IP/ATM/MPLS FPIDevelopment and delivery of Functional Programming Interface software (in C) for Agere's APP5xx processors, along with micro-code for underlying fast path software. The fast path supported IP forwarding and ATM switching, compliant with various RFCs and TM 4.1 / I610 standards. Supported technologies included Ethernet, PPP, MPLS, AAL5, Buffer Management (WRED) and Traffic Shaping (WFQ) with control plane interface compliant with NP Forum (now Optical Internetworking Forum) standards.* DSP Audio CodecProgramming StarCore DSP processors to operate as an audio codec (G-728).
Feb 2001 - Jan 2007
6 education records
Dhruv Tripathi education
Master Of Technology (M.Tech.), Electrical And Electronics Engineering
Indian Institute Of Technology, Delhi
Bachelor Of Engineering (B.E.), Electronics Engineering
Pandit Ravishankar Shukla University
Education record
Kvcmm, Jabalpur Mp
Education record
Bsf School, Jammu
Education record
Khms, Delhi
Education record
Model Academy
FAQ
Frequently asked questions about Dhruv Tripathi
Quick answers generated from the profile data available on this page.
What company does Dhruv Tripathi work for?
Dhruv Tripathi works for Arm.
What is Dhruv Tripathi's role at Arm?
Dhruv Tripathi is listed as Principal Engineer at Arm.
What is Dhruv Tripathi's email address?
AeroLeads has found 1 work email signal at @intel.com for Dhruv Tripathi at Arm.
What is Dhruv Tripathi's phone number?
AeroLeads has found 2 phone signal(s) with area code 512 for Dhruv Tripathi at Arm.
Where is Dhruv Tripathi based?
Dhruv Tripathi is based in Austin, Texas Metropolitan Area, United States while working with Arm.
What companies has Dhruv Tripathi worked for?
Dhruv Tripathi has worked for Arm, Intel Corporation, Broadcom Inc., Lsi Corporation, and Cisco.
How can I contact Dhruv Tripathi?
You can use AeroLeads to view verified contact signals for Dhruv Tripathi at Arm, including work email, phone, and LinkedIn data when available.
What schools did Dhruv Tripathi attend?
Dhruv Tripathi holds Master Of Technology (M.Tech.), Electrical And Electronics Engineering from Indian Institute Of Technology, Delhi.
What skills is Dhruv Tripathi known for?
Dhruv Tripathi is listed with skills including Ethernet, Arm, Semiconductors, Firmware, Embedded Systems, Asic, Technology, and Intel.
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