Di Lan

Di Lan Email and Phone Number

R&D MEMS RF Engineer at II-VI Incorporated
Di Lan's Location
Warren, New Jersey, United States, United States
Di Lan's Contact Details

Di Lan personal email

n/a
About Di Lan

Di Lan is a R&D MEMS RF Engineer at II-VI Incorporated.

Di Lan's Current Company Details

R&D MEMS RF Engineer at II-VI Incorporated
Di Lan Work Experience Details
  • Ii-Vi Incorporated
    R&D Lead Mems Rf Engineer
    Ii-Vi Incorporated Sep 2019 - Sep 2022
  • Ii-Vi Incorporated
    R&D Mems Rf Engineer
    Ii-Vi Incorporated Oct 2017 - Sep 2019
  • University Of South Florida
    Graduate Research Assistant
    University Of South Florida Jun 2012 - Jun 2018
    Tampa, Florida, Us
    • Designed, fabricated and evaluated a passive diamagnetic sensor for structural health monitoring that has achieved ~1.5mV/µm sensitivity from 10 to 50 Hz, and 15dB higher signal-to-noise ratio than commercial piezoelectric sensor• Completed MEMS-based oscillator design using piezoelectrically-transduced ZnO-on-Si resonator and characterized its phase noise and frequency response. • Fabricated MEMS resonators at GHz frequencies in a class-1000 university cleanroom facility, which were designed and modeled using ADS and MEMS finite element methods (Coventorware), tested at wafer-level and PCB-level.• Gained multi-year cleanroom experience in photolithography, plasma cleaning, RIE, DRIE, metal and piezo material sputtering, profilometer, XRD, Scanning Electron Microscope (SEM) and Atomic Force Microscope (AFM). • Designed and measured 2-20 GHz a low-noise distributed amplifier with a flat gain of 11dB, input/output reflection less than -10dB and a 3dB mid-band noise figure by using Qorvo TQPED E/D pHEMT GaAs technology.• Designed class AB power amplifier that has 63%PAE and 44dBm output power using Qorvo-T2G4003532.• Designed and simulated a high performance two-stage bootstrapped GaAs comparator with a gain enhancement that achieves 339 pico-sec total propagation delay with 40mV input at 0.8GHz using Qorvo TQP25 technology.• Applied 3D printing for packaging and assembly of an oscillator composed of a MEMS chip and a MMIC chip over a fully printed low-loss substrate with printed chip-to-chip interconnects and RF probe pads defined by laser cutting.
  • Qorvo, Inc.
    Rf Design Engineer
    Qorvo, Inc. May 2017 - Aug 2017
    Oo
    • Created RF front-end module level ideal simulation in ADS as an infrastructure for real product design. • Worked on diplexer (B34 and B39) and triplexer (B34, B39 and B41F) design and integration on various layers of laminates with evaluation board using AWR, HFSS, and ADS.• Made probe tip measurements of a module die assembled on an evaluation board using VNAs so the performance of the filters (B1, B3, B7, B25, B30 and B66) and impedance presenting to the PA can be captured. • Supported the design of evaluation board for RF module testing.
  • Modelithics, Inc.
    Rf Engineer
    Modelithics, Inc. Sep 2012 - Dec 2016
    Tampa, Fl, Us
    • Assembled components with soldering iron, reflow soldering station, wedge bonder and ball bonder.• Designed TRL calibration standards and PCB fixtures for RF testing.• Performed SOLT, TRL and other calibration methods on Multical, Wincal XE and Maury ATS software. • Measured Equivalent Series Resistance, passive S-Parameter (resistors, inductors, capacitors, filters) measurements for ATC, AVX, Coilcraft, MuRata, KOA and etc. using 8753D and 8510C VNAs.• Performed 4-port passive S-Parameter measurements for AVX Couplers using Keysight N5227A PNA.• Performed active S-Parameter and noise parameter measurements.• Performed DCIV screening and pulsed IV measurements on wafer-level transistors and die-level transistors with wirebonds to testing 10mil alumina fixtures.
  • San Francisco State University
    Graduated Teaching Assistant
    San Francisco State University Feb 2010 - Jun 2012
    San Francisco, Ca, Us
    • Lab instructor for ENGR 357 (Basic Digital Laboratory)• Provided instruction to undergraduate students in basic digital circuit lab• Help students to familiar with digital trainer and Xilinx ISE Design Suit• Strengthened communication and explanation skills • Lab instructor for ENGR 445 (Analog Integrated Circuit Design)• Mentored undergraduate students in equipment operation and simulation skill• Teaching assistant for ENGR 205 (Electric Circuit) and ENGR 350 (Electromagnetics) • Tutor and grader
  • San Francisco State University
    Graduate Research Assistant
    San Francisco State University Jun 2009 - Jun 2012
    San Francisco, Ca, Us
    • Designed and demonstrated a versatile low-frequency (~100 Hz) wireless power transfer technology using showing negligible losses when the receiving coil is placed inside an implant-grade stainless steel tube.• Designed and optimized planar inductors to maximize its system gain for longer operating distance for implantable passive MEMS sensors using an equivalent circuit model and analytical expressions.• Designed and implemented a feed-forward controlled AC-DC boost converter for biomedical implants that converts 500mV AC signal to 5V DC with ~3mW power and estimated time average efficient of 75%.

Di Lan Education Details

  • University Of South Florida
    University Of South Florida
    Electrical Engineering
  • University Of South Florida
    University Of South Florida
    Electrical Engineering
  • San Francisco State University
    San Francisco State University
    Embedding System
  • San Francisco State University
    San Francisco State University
    Electrical Engineering

Frequently Asked Questions about Di Lan

What is Di Lan's role at the current company?

Di Lan's current role is R&D MEMS RF Engineer at II-VI Incorporated.

What is Di Lan's email address?

Di Lan's email address is di****@****-vi.com

What schools did Di Lan attend?

Di Lan attended University Of South Florida, University Of South Florida, San Francisco State University, San Francisco State University.

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