Dileep Kumar Yadav Email & Phone Number

Hi, I have 3+ years of professional experience as a Physical Design Engineer. Currently working for LeadSoc Technologies as a full-time employee.My skill set include working on block level implementation of a SOC sub-block.Executing PNR and Timing closure. Making optimized floorplan for highly dense macro dominated block, considering congestion factors.Proficient with below Tools:PNR/Timing Tool setInnovus - AdvancePrimetime - AdvanceTempus - IntermediateIC Complier 2 - IntermediatePhysical Verification (PV)Calibre (Mentor) - DRC/LVS/Antenna/Density1. Block Features worked on:-> 7nm design node-> Block with 2.1million Gate count-> Macro dominated design with SRAM Count 495.-> Frequency 600MHz-> Area: 1000.216x1700.16 (1.777mm^2)->Number of clocks: 4->Metal Layers: 132. Block Features worked on:-> 7nm design node-> Gate count : 2.5M-> SRAM Count: 371.-> Frequency: 0.6GHz-> Area: 1100.456x1500x789 (1.65mm^2)->Number of clocks: 4->Metal Layers: 133. Block Features worked on:-> Technology node 5nm-> Area: 595x605um-> Macro Count 14-> Instance Count 0.7M-> Frequency 2.1GHz4. Block Features worked on:-> Technology node 40nm-> Area: 570x600um-> Macro Count 34-> Instance Count 40k-> Frequency 830MHzLooking forward to grow in the industry and give best of my contribution for development of Physical Design Semiconductor Field.