A competent and passionate professional with a total of 9 years of experience in ASIC and FPGA Design Verification and skilled in the following categories - ✔️Expertise in design verification using SystemVerilog and UVM.✔️Extensively worked on SoC-level verification, Subsystem-level verification as well as IP functional verification.✔️Experience in verification of ASIC design and FPGA design flows.✔️Hands-on Experience and good understanding on Protocols like AXI3, AXI4, AHB, APB and I2C.✔️Experience in Debugging with Synopsys, Cadence, and Questa Tools✔️Experience in SOC design support✔️Involved in Full custom design from requirement analysis to development and support.✔️Version Control Tools: Clearcase & Perforce✔️Possess good Debugging skills.✔️Experience in Writing SystemVerilog Assertions(SVA) and meeting Code/Functional Coverage Goals.✔️Preparing TestPlan➕ Additional Info➡️ Possesses Good Communication and Problem-Solving Skills➡️ Believes in Progressive Learning and possesses a continuous learning attitude➡️ An Avid Reader focusing mostly on Self-improvement, Autobiographies/Biographies, and Philosophical books