Design Verification engineering for Wireless PHY

- Led Design Verification effort for ASIC in LiDAR sensor and worked with multiple vendor contractors to reach tape-out ready ASIC- Created in-house UVM verification environment allowing regression analysis and functional coverage collection & libraries for use on future projects- Caught bugs in post-synthesis netlist and worked with backend design vendor in China- FPGA & firmware(user-space application) design, simulation, integration testing of data packet time-related blocks- Creation of FPGA unit-test infrastructure for lidar data uplink / downlink blocks using Xilinx VIP

- 5G NR PHY Modem Algorithm & Microarchitecture development & optimization in Rx datapath (PDSCH)- RTL Design & Verification of modem block- and submodule-level and subsequent re-design/re-architect as per ASIC and FPGA specifications- Design Verification in Co-simulation verification environment & debugging in both reference model & RTL- FPGA synthesis & timing analysis to uncover worst timing paths & fix them- Design optimization to improve resource usage in FPGA- Gate-level simulation of synthesized netlist & debugging- Use of Spyglass toolset for Lint-ing and other source code analysis to root out bugs & fix them

- Design Verification: 1) Regression analysis, 2)Debugging of test failures, 3) Test creation & modification for tcl-based simulation environment- Worked on creation of FPGA simulation environment - created FPGA counterpart to RTL simulation- Chip Project Infrastructure: Initial chip project migration, git repository set-up and maintenance, chip-level and core-level compilation & elaboration- Managing chip project database for the backend team

- Lab Bringup & FA Debug: Run diagnostics, verify chip characteristics on bench (such as power consumption and other performance metrics), Debug FA parts from customers- Design Verification: Regression analysis, Debugging of test failures, including resimulation and waveform analysis- Integration of design blocks into new SoC projects

- RF characterization & evaluation of WLAN PCB boards-    Work with system, chip, and other teams involved in bringup of new chips & board designs-    Conduct experiments to optimize board designs-    Troubleshoot and debug testing and hardware issues

- Conducted research in prostate HDR brachytherapy treatment planning- Developed mathematical optimization models using code written in Matlab and C++- Tested model with patient data (DICOM format) from clinic treatment computers

- Participated in research in HDR brachytherapy treatment planning at UCSF Department of Radiation Oncology- Presented research poster to fellow students and professors involved in the program at a symposium

BerkeleyNominated and selected to help students during labs with techniques and understanding of conceptsDesigned practice questions for students and assisted in lectureAttended lectures and weekly TA meetings; Helped proctor examinations; Prepared lab practical exam

- Cleaned and stocked rooms; Transported specimens for lab analysis- Helped with patients (ran errands, transported scopes for procedures)