Design and verify functional blocks for a wide portfolio of mobile power management ICs. Experience in entire design process from systems definition and RTL implementation to synthesis and timing closure. Currently lead verification engineer for multiple digital blocks and cores in 4G/5G chipsets where I design UVM testbenches and architect extensive design+test automation flows. Excellent experience with pre-silicon test and debug, including SystemVerilog simulators, formal verification, test planning and project management. Broad experience with Verilog, CDC, linting, logic synthesis, STA, SystemVerilog, UVM, and extensive scripting.

Graduate Teaching Assistant in the School of Electrical and Computer Engineering for three classes in Audio Engineering. Responsibilities include assisting students with laboratory experiments, designing new experiments, and grading assignments (70+ students).

Intern in QCT Multimedia Hardware. Designed and validated a high-speed interface for streaming pixel data in smartphone camera hardware; Implemented design in VHDL and Verilog; Coordinated with multiple team leads to define verification testplan at module and system levels; Executed testplan with use of Synopsys Verdi and internal verification flows.

Learned about the large-scale compute/regression environment needed to support ASIC design and verification. Validated codeline stability for multiple graphics core projects with automated workflow processes. Triaged failures in the different codelines, which served as a good introduction to digital hardware design and test environments. Refined and fixed issues with a new build flow tool (Ruby-based). Developed solid UNIX skills and working knowledge of Perl, VBA, and MySQL.

Gained a good overallunderstanding of how PC components are utilized to design, test and certify cost effective and robust point of sale terminals. Performed a competitive analysis of terminal performance and power consumption, and supported functional and compliance testing of three new terminals.