Dmitry Golev Email & Phone Number

Санкт-Петербург, Россия

Санкт-Петербург, Россия

ASIC design Principal EngineerResponsibilities:• Technical requirements and HDL modules development;• debugging and verification;Under my guidance or by myself the following items were developed:• Some extensions to the cpu core were integrated and tested

Russian Federation

- FPGA project management, design, optimization and integration.- DSP system development- Analytical calculations and simulation models development

Санкт-Петербург, Россия

ASIC design Principal EngineerResponsibilities:• Technical requirements and HDL modules development;• debugging and verification;• taking part in constraints development;• Netlist preparation and BE team support.Under my guidance or by myself the following items were developed:• Fine Time Measurement module for the distance estimation between stations;• Automation:o CDC violations report analyzis for nelist;o Memory instances and their clock signals list preparation using simulation data;o Documentation for Verilog modules (ports information and comments parsing and offloading to the Confluence).