As a part of Intel Validation Engineering Team- Worked on Prototyping of Intel Client CPU. - Creating FPGA Models for Hybrid FPGA integration platforms. - Working across driver, firmware and design Team

- Responsible for architecture design specification of in house FPGA transactors for in house protocols- Understanding of PCIe & CXL Protocol - Writing Verilog code- Working with verification Team for Writing Test Plan- Debugging and resolving customer and test bugs- Deployment & Integration of transactors across internal projects

* Responsible for testing multiple Features of Protium Tool like Memory Mapping on FPGA's, External SRAM Memory solution, Resets, Probes, Synthesizable System Verilog constructs etc. * Writing Synthesizable designs for Xilinx Virtex UltraScale Devices and using these designs to test the Protium Tool.* Working with Application Engineer's to understand customer issues and creating small designs to reproduce the issues, closely working with R&D and getting the issues resolved. * Working with AE's to bring up the performance of customer design by analyzing Critical Path Reports, placements and timing reports and suggesting improvements in constraints and tool's instrumentation. * Debugging issues on ChipScope and suggesting improvements in placement and timing.* Handling Regression Suites and Infrastructure and writing scripts to automate day-to day tasks. * Understanding Customer Requirement, identifying use-models and utilities and writing F-Spec for R&D To develop new Feature. * Brought up AHB Lite and I2C Protocol as a part of an internal Project on Protium Tool.

Build Engineer for Spyglass Tool , Automating Build scripts of SpyGlass in C Shell & Perl.

Details: The project involves writing RTL code & developing test environment of 8051 micro-controller(Instruction set & Bus Interface.) in Verilog & System Verilog and also analysing simulation results shown NC Sim (Simulation Tool by Cadence) with respect to Intel 8051 specifications.