Doug Good Email & Phone Number

Austin, TX, US

Austin, TX, US

Santa Clara, California, US

Led global teams in the verification of several large subsystems used in theIntel Xeon product line. Subsystems include CXL/PCIe interface IPs, and various computational and data transfer acceleration engines.

Santa Clara, California, US

Specified and implemented the performance verification of an Intel Omni-PathHPC fabric SOC.

Austin, Texas, US

Built and led a team of 20 engineers in a large-scale SOC verification effort. This project was a first-pass success (no silicon respin) and exceeded the goals set at project outset.Verified the SOC Power Management Unit integration using C-based tests, SystemVerilog/UVM, and property-checking formal methods.

Santa Clara, California, US

• Senior manager and lead verification engineer
• Led a global team of over 50 engineers in the verification effort for the lowpower x86 microprocessor core used in AMD's C and E series APUs.- First-pass success. Initial revision delivered to customers.
• Led the SOC integration effort for the first AMD Fusion APU.
• Played a key role in the modernization of AMD's corporate verificationmethodology for current and future AMD x86 microprocessors.
• Defined and installed the verification flows and methodologies for fivemicroprocessor design efforts.
• Led the team’s recruiting effort which resulted in over 25 hires.

US

• Participated in all phases of verification of five microprocessors.
• Verified the core ALU and pipeline logic for Intrinsity’s 2+GHz MIPS-basedadaptive signal processor (ASP). Much of the testing was performed usingObsidian Software’s Raven directed random test generation tool.
• Assisted in verification of the ASP matrix co-processor.
• Designed and implemented the chip-level simulation test bench in addition toseveral module-level test benches.
• Designed and implemented the software environment for silicon bring-up tests.
• Participated in lab bring-up and validation of processor silicon.

• Verified the interrupt controller for a PowerPC north bridge interface ASIC.

Cupertino, California, US

• ASIC Design verification for Tandem’s next-generation fault-tolerant computers.
• Led a team of nine engineers to verify an i960 bus-to-ServerNet bridge ASIC.Verification was performed in both simulation and QuickTurn emulation with aheavy reliance on random stress and formal code inspections.
• Performed silicon bring-up of a VMEbus interface ASIC. Developed bring-uptests and performed signal quality analysis and voltage margining.
• Verified a VMEbus-to-ServerNet interface ASIC using QuickTurn emulationand Verilog simulation. This ASIC shipped in first-pass silicon.
• Verified cache coherency and PCI-to-ServerNet ASICs in emulation.

• Random Technology was a three-person business which provided specialpurpose I/O interface devices.
• Designed and routed three printed circuit boards using surface-mount andthrough-hole technologies. Components include a 68306 microprocessor,DRAM, ROM, and a component modem.
• Wrote Class 1 fax software to control an embedded modem.
• Over 600 units delivered to the customer,

• Technical lead for hardware simulator development and maintenance.
• Solely responsible for creating the proprietary system-level hardware simulatorused in the development of a mainframe computer.
• Led a team of engineers in the design and implementation of a tool thatconverted gate-level netlists into high-performance C language models.
• Received several awards from peers and management for leadership andperformance.
• Member of the K-1 supercomputer design team.
• Specified, implemented, and maintained CPU, SMP, cache, and memorysystem verification tests and diagnostics for a scalar supercomputer. Testcode included over 70,000 lines of K-1 architecture assembly language.

Arlington, VA, US

• Defined software requirements for the in-flight test avionics of military aircraft.
• Solved problems related to avionic systems found during flight.
• Verified that avionic systems met built-in-test design requirements.