Don Gee
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Don Gee Email & Phone Number

Senior Staff ASIC Design at Cirrus Logic
Location: Chandler, Arizona, United States 9 work roles 2 schools
1 work email found @qualcomm.com 2 phones found area 480 LinkedIn matched
✓ Verified August 2026 4 data sources Profile completeness 86%

Contact Signals · 1 work email · 2 phones

Work email d****@qualcomm.com
Direct phone (480) ***-****
LinkedIn Profile matched
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Current company
Role
Senior Staff ASIC Design
Location
Chandler, Arizona, United States
Company size

Who is Don Gee? Overview

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Don Gee is listed as Senior Staff ASIC Design at Cirrus Logic, a with 1760 employees, based in Chandler, Arizona, United States. AeroLeads shows a work email signal at qualcomm.com, phone signal with area code 480, and a matched LinkedIn profile for Don Gee.

Don Gee previously worked as Senior ASIC DSP at Qualcomm and Senior ASIC DSP at Qualcomm. Don Gee holds Mse, Ee Communications from Arizona State University.

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{first_initial}{last}@qualcomm.com
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Profile bio

About Don Gee

Technical and managerial lead on ASIC IP development teams with process experience from frontend up to physical design. System level and ASIC experience of specifying, micro-architecting, verifying, constraining and implementing ASIC/FPGAs in the areas of Digital Signal Processing (DSP). Specification includes development of math equivalent or sample accurate models when compared to RTL and functional coverage for ASIC first-time tape out success. Experience in designs include micro-architecture, code and verification of radio digital pre-distortion (Bluetooth), audio processing (Audio Earbud and Speaker), signal detection (Satellite Payload), PSK communication (Small Deep Space Transponder), Error Correction (Viterbi Decoder), GPS Coder/Correlator (Global Positioning), Echo Canceller (Cellular Basestation), Mobile Multimedia JPEG/MPEG Accelerator (Video CODEC), Video Display and Graphics (Video Processing). Moreover, experiences in low power interface designs for cellular, including code and verification of AMBA interfaces, UART, Serial/Parallel, GPIO, LCD Drivers. Heavy implementation experience in front-end ASIC design/verification using methodologies for deep submicron (6 nm, 14 nm, 0.25 um, 0.l8 um, and 0.13 um) technologies. Performed verification, synthesis and validation utilizing UVM, LEC, Constraint Development, Static timing, FPGA prototyping, Hardware accelerators, and PLI interfaces. Experience in system modeling in Matlab for audio processing, mixed signal digital pre-distortion algorithms, Signal FFT and filtering, 8-VSB Digital Television source encoding, Virterbi decoding. Have had Secret Security Clearance.

Current workplace

Don Gee's current company

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Cirrus Logic
Cirrus Logic
Senior Staff ASIC Design
Chandler, AZ, US
Website
Employees
1760
AeroLeads page
9 roles

Don Gee work experience

A career timeline built from the work history available for this profile.

Senior Asic Dsp

Chandler, Az, Us

Senior Asic Dsp

San Diego, Ca, Us

Specify, design, and verify digital signal processing ASIC components for use in mobile, automotive, and home entertainment systems* Matlab modeled, specified, designed and implemented in RTL an Audio Signal Processing (ASP) unit for interpolation and equalization filtering incoming digital audio signals. Utilized a custom processor containing multipliers and a single accumulator that was programmable via configurable sequence state machines* Micro architecture design digital processing elements for Bluetooth radio transmission and reception, power management, AD converters and clock synthesizers in mixed analog and digital IP.

Nov 2011 - Oct 2023

Systems Engineer

Fairfax, Va, Us

Specification, modeling, design and verification of signal processing ASIC/FPGAs (~15K to ~1.5M gates)* System engineer responsible for creating specifications and mathematically true Matlab models for FPGA and ASIC digital signal processing designs. Created five different specifications and models for five different projects. Responsibilities included micro-architecting DSP structures such as FIR filters and FFTs. Responsibilities included technical team leadership and customer presentations.* ASIC designer for Small Deep Space Transponder ASIC containing BPSK receiver with carrier tracking loop and decoder and GMSK modulation coder. Created Matlab BPSK modulator model for generating test vectors.* Sole FPGA architect, designer, and verifier of custom Virterbi Decoder for error correction. Created mathematically true Matlab model of design and coded in Verilog.

Jun 2003 - Oct 2011

Fpga Engineering Consultant

Three Five Systems

Provided VHDL design experience for engineering team that supports sales staff selling LCD, CSTN, TFT, OLED displays. Using Modelsim for design and verification and Xilinx ISE for CPLD implementation.

Mar 2003 - May 2003

Senior Asic Engineer

Netergy Microelectronics

Designed, verified, and prototyped for Video over IP ASIC (~ 1.5 M gates):*Video Display Unit processes Y, Cb, and Cr image data for display on NTSC/PAL displays or LCD displays. Processing includes synchronization generation, 4:2:0 to 4:2:2 conversion, spatial filtering, and color space conversion. Unique and flexible design utilizes shared hardware for processing NTSC/PAL and any standard definition LCD timing.*Video Graphics Unit retrieves and renders sprites according to customizable command stream control. Sprite rendering functions include palette table look-up, 4:2:0 to 4:2:2 conversion, horizontal polyphase filter scaling, alpha blending, and edge filtering.

Feb 2002 - Feb 2003

Senior Asic Engineer

Luxxon Corporation

Designed, verified, and prototyped for Multimedia Processing ASIC (~500K gates):*Hardware Acceleration Unit for JPEG/MPEG-4 algorithms in low power devices. Accelerator contained video processing and digital signal processing functons for performing video CODEC algorithms for compression/decompression.

May 2000 - Feb 2002

Asic Engineer

Motorola Inc

Modeled, designed, verified designs for ASICs:*Modeled portions of Digital Video Broadcasting (DVB) and 8-VSB source encoding ASIC designs.*Cellular devices interface ASIC (~22 K Gates) containing LCD Driver, UART, GPIO, Key Scan, Watch Dog functions.*Cellular infrastructure baseband ASIC (~250 K Gates) containing Echo Canceller algroithm uniquely architected for multiple channels - US Patent(#5,856,970)*Coder/Correlator ASIC (~70 K Gates) for satellite Global Positioning System receiver

Jan 1988 - May 2000
Team & coworkers

Colleagues at Cirrus Logic

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2 education records

Don Gee education

Mse, Ee Communications

Arizona State University

Bs, Ellectrical Engineering

University Of Arizona
FAQ

Frequently asked questions about Don Gee

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What company does Don Gee work for?

Don Gee works for Cirrus Logic.

What is Don Gee's role at Cirrus Logic?

Don Gee is listed as Senior Staff ASIC Design at Cirrus Logic.

What is Don Gee's email address?

AeroLeads has found 1 work email signal at @qualcomm.com for Don Gee at Cirrus Logic.

What is Don Gee's phone number?

AeroLeads has found 2 phone signal(s) with area code 480 for Don Gee at Cirrus Logic.

Where is Don Gee based?

Don Gee is based in Chandler, Arizona, United States while working with Cirrus Logic.

What companies has Don Gee worked for?

Don Gee has worked for Cirrus Logic, Qualcomm, General Dynamics Ais, Three Five Systems, and Netergy Microelectronics.

Who are Don Gee's colleagues at Cirrus Logic?

Don Gee's colleagues at Cirrus Logic include Phillip Kan, Neil Whyte, Weichun (Tracy) Juan, Zhen-Ting Huang, and Randy Stephens.

How can I contact Don Gee?

You can use AeroLeads to view verified contact signals for Don Gee at Cirrus Logic, including work email, phone, and LinkedIn data when available.

What schools did Don Gee attend?

Don Gee holds Mse, Ee Communications from Arizona State University.

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