Don Matthews Email & Phone Number

Longmont, CO, US

Santa Clara, California, US

• Job Responsibilities:I exhibit my extraordinary expertise in overseeing AMD's post-quantum cryptographic (PQC) analysis and contribute to NIST 800-208 review. Moreover, I create and execute AMD's PQC roadmap.
• Conducted a thorough review of AMD's RNG implementation, improving security by aligning the x86 microcode RD-RAND and NIST 800-90 TRNG with the respective requirements of their distinct use cases in the x86 and.
• Enhanced AMD memory encryption by designing high-performance solutions with multiple keying options, significantly improving system security and optimizing key selection within the existing encryption engine.
• Developed a hardware-based key rolling solution on AMD interconnects (adopted by Ultra Ethernet), preventing side-channel attacks and enabling seamless key updates without software/firmware intervention.
• Advanced security standards for PCIe IDE, PCIe TDISP, SPDM, CXL TSP, UltraEthernet, and UALink, ensuring standards industry security needs were met with simple, robust solutions.
• Improved key management efficiency by inventing clustered keying, allowing multiple devices in a security association to share a global key, saving keying space.

Arlington, VA, US

• Job Responsibilities:During this job role, I performed security assessments of existing designs, identifying vulnerabilities and working with design teams to implement updates that meet performance and security.
• Enabled line-rate operation for memory encryption and authentication by re-architecting the unit with a key generator producing a key per cache line and per write operation.
• Passed government lab reviews for anti-tamper compliance with the development of a custom key generation algorithm.
• Reduced system complexity and enhanced security by analyzing and recommending improvements to military communication security protocols.
• Enhanced security against side-channel attacks by creating a fast, high-performance key generation algorithm for unique keys per memory block and write operation while meeting stringent anti-tamper requirements.
• Eliminated security vulnerabilities with an "in place" (area and performance) redesign of the secure memory transaction unit during a chip spin.

Fremont, CA, US

• Job Responsibilities:Managed hardware security architecture and design for cryptographic features across all products, including rotational media and SSDs. Contributed to SSD ASIC controller architecture, focusing on.
• Designed mechanisms for internally generating and burning random numbers into one-time programmable memory for root key security
• Defined and implemented security requirements for full disk encryption on SSD controllers, addressing flash-specific vulnerabilities and ensuring secure data overwriting on "dead" flash pages
• Achieved optimal hardware/firmware trade-offs while leading hardware design/security analysis for security architecture team
• Enhanced metadata processing efficiency by architecting an offload engine that automatically retrieves sector metadata from external memory, optimizing hardware/firmware division
• Accelerated RSA encryption engine design, defining capabilities, algorithms, and interfaces, and collaborating with verification teams to achieve 50x faster simulation times

Ms, Electrical Engineering

Bs, Computer Science