Donglai Dai Email & Phone Number

California, United States

Columbus, Oh, Us

• Deliberate and set company long term directions and strategies for RISC-V based IoT products. Raise funds and work through investment due diligence. Hire, build, and motivate a capable team with a common vision.• Set up partnerships for chip backend design, fabrication, packaging, and product testing. Set up and supervise supply chain operations. Supervise and support the product marketing and sales team. • Make detailed plans and manage chip R&D projects. Lead all front-end design duties including product definition, architecture, microarchitecture, RTL implementation, and IP integration, function verification, and FPGA emulation, enabling compiler/drivers/libraries and system IDE tools. Coordinate backend design and interact with fab venders.

Santa Clara, California, Us

Architecture, Product Development Group (PDG); Platform Engineering Group (PEG) Architectural owner of global time synchronization (similar to IEEE 1588v2) for all Intel product lines including Xeon Phi, Xeon server/micro-server, Xeon client, Atom SoC, BaseIA IoT (Internet of Things). Collaborated with key stakeholders in usage model, application, product planning, platform architecture, design execution, and implementation. Wrote architecture specifications and organized formal reviews.

Santa Clara, California, Us

SoC Architecture and Performance; Intel Architecture Development Group (IDG) Managed and led team of architects and engineers building FPGA prototypes of Intel Atom SoC products for smartphones and tablets, modeling, exploring and validating SoC performance and power trade-offs. The software/hardware co-emulation prototypes was used as a realistic platform for early software and firmware development and debugging; enabling pre-silicon and post-silicon validation driven directly by end-use cases.

Santa Clara, California, Us

Platform Architectural Research, Microprocessor and Programming Research (MPR) Lab Represented architecture and front-end design team in internal and external meetings and discussions, part of joint pathfinding task force for on-chip interconnects for many Intel core microprocessors. Defined technical direction, provided leadership and made hands-on contributions in network-on-chip research.

Houston, Texas, Us

Hardware Engineering DivisionArchitect of Cray Cascade project sponsored by DARPA HPCS program, Dept of Energy (DoE). Defined instruction set architecture (ISA) of Cray’s vectorized multi-threaded parallel processing system. Represented architecture and logic design team interfacing with OS and compiler teams.

Milpitas, Ca, Us

Architecture and Logic Design, Engineering and DevelopmentArchitect and design lead in SGI Ultraviolet project, defined feature set and functional requirements, wrote architecture specifications of the hub chip, router chip, and communication protocols, performed high-level modeling and simulation (in C/C++), evaluated performance and trade-off options, developed micro-architecture, implemented the RTL code, debugged and validated the design with extensive coverage using direct and random tests.

Ph.D., Computer Sciences

Master Of Science (M.S.), Computer Sciences

Bachelor Of Science (Bs), Computer Sciences And Engineering