Don Pearce Email and Phone Number
Digital IC Design Engineer/Manager | ASIC Design | Digital RTL design | Team Leader at
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NXP Semiconductors
High Tech Campus 60, Eindhoven, Noord-Brabant 5656 AG, us
Don Pearce's Location
Austin, Texas Metropolitan Area, United States, United States
Don Pearce's Contact Details
Don Pearce work email
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Don Pearce personal email
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About Don Pearce
Professional engineer with 23+ years in ASIC design with an emphasis on digital flows with analog integration. Fully adept in the entire mixed-signal ASIC design flow, from product definition, design and implementation, silicon bring-up and through introduction. Proven highly effective leader and team collaborator, able to bring multi-disciplines together to assure on-time delivery with Rev-A success. • 25+ years of experience with Verilog RTL coding, including influencing/writing RTL Coding Guidelines, LINT rules, coding for re-use, coding for testability • 23+ years of experience working with mixed signal ASICs with on-board CPU/MCU and partitioning functionality between FW/HW including post-Si bug work-arounds in FW • Lead engineer on over 12 full cycle mixed signal ASIC from spec to introduction including: customer requirements/tradeoffs, RTL coding/lint, top level chip stitching, CDC, custom floorplanning, memory generation, synthesis, DFT insertion, ATPG, directed DV, CTS/APR planning/guidance, STA, ECOs, PG, Si bring up, FIB debug, correlation, characterization, test reduction, and introduction • Energetic team player with a recognized ability to motivate and lead by example.
Don Pearce Work Experience Details
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Technical Director - Chip LeadNxp Semiconductors Jun 2023 - PresentEindhoven, Noord-Brabant, NlChip Lead for the Microcontroller/Microprocessor Engineering Group (MME) -
Senior Principal Design Engineer/ManagerSkyworks Solutions, Inc. Dec 2021 - Jun 2023Irvine, California, UsTeam lead for CPU/MCU processor development/integration group to support audio/AI products within Skywork's AIS group. Responsible for hiring, training, and retaining top engineering talent.• Establish processor roadmap for AIS products.• Evaluate processor IP for PPA objectives for given process nodes.• Integration of dual processors for next-generation dual-radio audio processor targeting gaming headset applications.• Hands on technical developer involved in front-end digital chip (mixed-signal) development (RTL to Netlist) -
Senior Principal Design EngineerSkyworks Solutions, Inc. Sep 2019 - Dec 2021Irvine, California, Us• Hands on technical developer involved in front-end digital chip (mixed-signal) development (RTL to Netlist) for custom silicon chip targeting Tier 1 customer, targeting TSMC 40nm process.• Developed key RTL modules interfacing with analog and digital datapaths of a highly efficient class-D headset amplifier.• Key contributor to digital engineering hiring process.
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Senior Staff Engineer/ManagerQualcomm Jul 2017 - Sep 2019San Diego, Ca, UsHands on technical lead involved in all aspects of chips development (RTL to GDS) for mixed-signal digital charger IP for PMICs/SMBs chips. Direct management of a team of 5 digital design engineers. -
Rtl Design EngineerSamsung Aug 2016 - Jul 2017Responsible for RTL design and implementation of custom network-on-chip interfaces for next generation GPU memory sub-system. GPU is designed as soft-IP for hand-off to hardening team targeting Samsung’s latest production node <10nm.• Implemented all NOC interfaces between low-level graphics modules and L1-cache, between L1- and L2-caches and L2-cache and ACEM• Implemented Atomic Scalar and Vector operations in custom ALU module• Improved RTL code for compliance with lint and synthesis • Optimized RTL code for timing target of 750MHz• Worked with FDV and PPA teams to triage bugs and improve system performance
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Staff Digital Design EngineerIdt - Integrated Device Technology, Inc. Jan 2016 - Aug 2016San Jose, Ca, UsResponsible for RTL design and implementation of DDR4 data buffer logic targeted to TSMC 40nm process • Implementation of math calculations for on-the-fly timing calibrations for optimal timing of R/W operations • Applied consistent RTL coding style to current design • Addressed numerous lint errors and warnings • Delivered feature improvement of buffer timing per customer requirements. -
Ic Design ManagerCirrus Logic May 2011 - May 2014Austin, Tx, UsResponsible for RevA delivery of mixed-signal silicon to Tier 1 customer from definition to productization. Managed proprietary SerDes IP and MCU system and the respective development teams. Managed cross-functional IC development schedules and providing weekly project status for executive review. Responsible for the development and retention of design team. • Led design team to tape-out CS46L02 per customer requirements, silicon delivered to customer for Rev A production • Delivered 55nm port of proprietary SerDes IP to design team for CS46L04, first pass silicon success • Delivered first MCU-based sub-system to design team for CS46L04, first pass silicon success • Responsible for the selection and license agreement of 8051 MCU IP for use in multiple custom ICs • Contributed to a standard RTL lint rule set approved by committee and deployed across the division • Achieved 100% desired staff retention • Hired 8 cross-functional engineers (analog, digital, firmware) to complete mixed-signal team of 12 • Delivered CS46L01 to production, on-time and first-pass success per customer requirements -
Principal Mts - Ic DesignMaxim Integrated Products Aug 2005 - May 2011San Jose, Ca, UsChip lead for multiple MCU-based ASICs targeted to various internal and external processes. Responsible for all aspects of front-end integration of ASIC: RTL, simulation, synthesis, STA, floorplanning, memory generation, test, etc. Provided team leadership for younger engineers and support staff(firmware, analog designers, test, systems). Performed silicon validation through characterization, qualification and introduction.“Green Hornet” – Chip lead for wide operating range (1.0-3.6V) Infrared ASIC targeted to 0.18 um TSMC processMAX1740 Design Team – Chip lead for novel magnetic strip card reader ASIC targeted to 0.18 um TSMC processMAX1441 Design Team – Chip lead for a capacitive touch sensor microcontroller targeted to an internal Maxim process. MAXQ610 Design Team – Individual contributor responsible for IR Timer sub-block design. DS8500 Design Team – Individual contributor responsible for FTEC. MAX2990 Design Team – Chip lead for robust power-line modem microcontroller targeted to 0.18um TSMC process. MAXQ1103/1959 Design Team – Individual contributor responsible for implementing the Dallas 1-wire interface on a crypto-microcontroller flip-chip in a Dallas Semiconductor iButton. This implementation is Dallas Semiconductor’s first design to implement this function completely in Verilog RTL. I added functionality to improve the bus performance of the 1-wire interface to 1Mbps, while still allowing for legacy compatibility. -
Principal Design EngineerMicrochip Technology, Inc Apr 2003 - Aug 2005Chandler, Az, UsDigital chip lead for multiple MCU-based ASICs targeted to various internal processes. Responsible for all aspects of front-end integration of ASIC: RTL, schematic capture, analog-top integration, simulation, synthesis, STA, floorplanning, memory generation, test, etc. Provided team leadership for younger engineers and support staff (firmware, test, systems) both on-site and remotely.18F46K20 (Copper) Design Team – Digital lead for the product vehicle used to prove Microchip Technology’s new 200K internal fab process. In addition to full chip design, synthesis, STA and APR, I had 2 engineers focused on simulations reporting to me.18F46K20 Design Team – Digital lead for the product vehicle used to prove Microchip Technology’s new 185K internal fab process. In addition to full chip design, synthesis, STA and APR, I had 3 engineers focused on simulations reporting to me.PS800 Design Team – Key digital designer for the PS800 product family. In addition to digital lead responsibilities, I designed a custom serial interface peripheral, including a slave SMBus/I2C serial interface with a single pin serial communication option.PS500 Design Team – Integrated PIC microcontroller into the first PowerSmart precision analog circuitry for battery management. As the veteran Microchip designer, I brought the team together to bridge the analog, digital and firmware together to form a complete solution. I was the key digital designer to incorporate the analog periphery into the PIC architecture including top-level schematic capture, redesigning the port circuitry using RTL, setup and implement all digital simulations, and train the design group on the PIC architecture. -
Senior Design EngineerMicrochip Technology, Inc Jan 2001 - Apr 2003Chandler, Az, UsIndividual contributor for multiple MCU-based ASICs targeted to various internal processes. Responsible for schematic capture, RTL, simulation, debug and triage, APR and floor planning.18F8680 Design Team – First PIC microcontroller to incorporate the Enhanced CAN peripheral. • Implemented control logic for eCAN peripheral in RTL and verified by simulation. • Synthesized full eCAN (Control and datapath), creating constraints and exceptions. • QC of third-party CAN engine IP from Sci-Worx. • Designed FPGA prototype board to interface with the MPLAB ICE for early FPGA emulation of eCAN peripheral (and entire MCU)18F8720 Design Team – Design and debug of various peripheries on largest memory MCU from Microchip. • Tested all timers and serial communication ports • Implemented ECNs for design changes from schematic capture to custom layout
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Senior Design EngineerHoneywell Technology Aug 1999 - Jan 2001Charlotte, North Carolina, UsLead Logic Designer for avionics cockpit embedded system platform with one reporting designer. I was responsible for the design of multiple logic devices from concept to implementation. Additional responsibilities include: VHDL process development and coding standards, working directly with vendors and suppliers from prototype development to production cost contracting, supporting marketing trade shows.• Reverse engineered driver chip for custom polysilicon LCD, implementing the logic required to control RGB A/D video conversion• Micro-architected CPU interface device for Motorola PowerPC 8240/5 CPU with various memory and I/O. -
Design EngineerRockwell Collins Dec 1997 - Aug 1999Cedar Rapids, Iowa, UsEthernet Switch Design Team – FPGA design architect of an implementation of a local bus controller for an Ethernet Switch System. LFDS Design Team – Lead PCB designer for the ADIO card used in the DCC as a part of a triple-redundant cockpit display computer system for Boeing 767-400ER aircraft. Captured all requirements and implemented design with traceability via DOORs. I had complete oversight over board design, lab testing, and manufacturing bring-up.CSEL SAASM Design Team – Validation engineer for CSEL/SAASM GPS Handheld radio. Held Secret Security clearance for this work.
Don Pearce Skills
Rtl Design
Mixed Signal
Asic
Ic
Power Management
Cmos
Semiconductors
Soc
Analog Circuit Design
Verilog
Low Power Design
Integrated Circuit Design
Analog
Cadence Virtuoso
Static Timing Analysis
Hardware Architecture
Dft
Circuit Design
Primetime
Systemverilog
Simulations
Digital Signal Processors
Rtl Coding
Signal Integrity
Microprocessors
Debugging
Eda
Vlsi
Physical Design
Timing Closure
Functional Verification
Spectre
Physical Verification
Logic Synthesis
Pll
Bicmos
Cadence
Spice
Tcl
Fpga
Modelsim
Processors
Logic Design
Silicon
Team Management
Project Management
Project Planning
Cross Functional Team Leadership
Don Pearce Education Details
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The University Of Texas At DallasElectrical And Electronics Engineering -
Kansas State UniversityDigital Systems
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Johnson County Community CollegeGeneral Studies And Humanities
Frequently Asked Questions about Don Pearce
What company does Don Pearce work for?
Don Pearce works for Nxp Semiconductors
What is Don Pearce's role at the current company?
Don Pearce's current role is Digital IC Design Engineer/Manager | ASIC Design | Digital RTL design | Team Leader.
What is Don Pearce's email address?
Don Pearce's email address is do****@****mily.us
What schools did Don Pearce attend?
Don Pearce attended The University Of Texas At Dallas, Kansas State University, Johnson County Community College.
What skills is Don Pearce known for?
Don Pearce has skills like Rtl Design, Mixed Signal, Asic, Ic, Power Management, Cmos, Semiconductors, Soc, Analog Circuit Design, Verilog, Low Power Design, Integrated Circuit Design.
Who are Don Pearce's colleagues?
Don Pearce's colleagues are Andre Vullhorst, Harsh Tyagi, Antoria Hsu, Albert Moiceanu, Torsten Voss, Karel Krehlik, Jerry Wang.
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