Doris Hill Email & Phone Number

Koto-Ku, Toyosu, Tokyo, Jp

• Lead layout designer• Perform top level hook up and verification that were critical in ensuring design functionality • Perform chip floor planning • Assign work to offsite layout designers • Track the layout design for progress status• Perform layout review from cell level to top level to ensure high quality work• Layout of AMP, OSC, PLL, BANDGAP, LDO, ADC and PADRING cell in 35nm process providing circuit optimization for peak performance• Work closely with the engineers to ensure the layout meets the design requirements • Assist engineers with problems on DRC, LVS, floor plan of cells or parasitic extraction• Work closely with EDA team to identify and fix design bugs before tape out submission• Collaborate with offsite layout designers in different time zones to meet layout requirement• Mentor layout designers in different time zones on layout practices• Set up new layout methodology which is followed across the sites which helps in good quality layout and efficient execution.• Review fractured data ensuring accurate layers submitted for PG

Dallas, Tx, Us

• Lead layout designer• Performed top level hook up and verification that were critical in ensuring design functionality • Performed chip floor planning • Assigned work to offsite layout designers • Tracked the progress of the layout and schematic for the design progress status• Performed layout reviews from cell level to top level to ensure high quality work• Layout of TX, RX, PPA, and DAC cell in 45nm process providing circuit optimization for peak performance• Worked closely with the engineers to ensure the layout meets the design requirements• Performed parasitic extraction to be placed in simulation • Assisted engineers with problems on DRC, LVS, floor plan of cells or parasitic extraction• Worked closely with EDA team to identify and fix design bugs before tape out submission• Collaborated with offsite layout designers in different time zones to meet layout requirements• Mentored layout designer in different time zones on layout practices• Set up new layout methodology which is followed across the sites which helps in good quality layout and efficient execution.

Wilmington, Ma, Us

Wilmington, Ma, Us

Senior Layout Designer•Performed top level hook up and verification that were critical in ensuring design functionality •Perform chip floor planning •Achieve layout review from cell level to top level to ensure high quality work•Layout of Buck regulators, VCO, LDO, Band gap, Drivers, DAC, PLL, digital logic and pad ring cell in 0.18 to 0.25 process providing circuit optimization for peak performance•Mentoring on layout practices and cadence tools increasing the knowledge of the team•Submitted data for tape out of chip to secure chip completion•Archived files for back up usage•Scheduled in-house training to build confidence in job knowledge•Deliver parasitic extraction to be placed in simulation •Designed layout that was robust, possessed functionality, and area efficient contributing to DEPL and PMP product development•Identified and participated in the development of new or improved layout methods and design flows leading to increasing layout design productivity•Evaluated new CAD tools to identify errors/accurate before release to full development•Work remotely with other site

Senior Layout Designer•Designed custom layout of RF and analog circuits on CMRF7SF process for accurate layout•Layout interface to IBM foundry support improving the PDK•Developed layout checklist improving the quality and consistency of lessons learned•Participated in methodology structure providing infrastructure for the company database•Performed floor planning and pad ring layout to ensure package

Dallas, Tx, Us

IC Layout Designer•Performed layout from cell level to top level using analog, RF BICMOS, and RFSIGEI 0.35 process contributing to the transceiver and receiver products•Set up database for projects and directory back up•Utilized silicon ensemble for generation of auto place and route blocks•Coordinated zebra PG sharing which reduced the cost of PG between several groups•Reviewed fracture data ensuring accurate layers submitted for PG

•Taught CMOS processing/mask fundamental and terminologies providing an understanding of the layout process from start to completion •Taught schematic and logic conversions, stick planning, design rules and layout to schematic verification to expand knowledge of the layout functional process

IC Layout Designer (June 1999 to July 2000)•Performed layout for the micro controller group•Planned layout of custom digital and analog blocks •Verification of cell for functionality using DRACULA•Performed back annotation of layout to develop a schematic

A.A.S, Computer Aided Design And Drafting Integrated Circuit Design

A.A.S, Electronic Technology