Doug Macintyre Email & Phone Number

Marlborough, Ma, Us

Maynard, Ma, Us

ASIC Hardware Engineer with primary responsibility of supporting customers integrating Acacia DSP ASICs for long haul and DCI into their designs. Emphasis on high speed interfaces, control loops, layout, power supply and noise issues. Also presented to customers, participated in design reviews, and traveled to both customers and suppliers as required.

Espoo, Southern Finland, Fi

Led teams of up to 10 engineers through numerous Ethernet core and edge switch products.Partnered with Senior Management in design process definition. Represented hardware engineeringto all other major internal functions including software, regulatory, test, technical publications,quality and supply chain.· Delivered line of 10 optical-line interface (PHY) cards on schedule by managing team of 10designers, leveraging and reusing major design blocks.· Provided critical signal integrity support that facilitated development of 20 card types formulti- chassis ATM switch by recruiting / staffing Signal Integrity Team of 5 members. Managedwork assignments, model library maintenance and verification process.· Created / delivered 3 successful backplanes as part of Architecture Team by contributing toconnector placement, pin-out and routing concepts while managing team of 3 backplanedesigners.· Contributed to successful product design in subsequent programs by managing outsourcedresources for both thermal and mechanical design.· Enabled successful deployment of Field Programmable Gate Array (FPGA)-based, 2.5G perthread, distributed switch fabric in CBX3500 switch acting as principal technology evaluator forIC vendors offering integrated serdes technology.· Fulfilled customer availability requirements by acting as individual contributor in areas suchas timing switchover circuitry for redundancy where staff analog / linear expertise was lacking.

Established and ran SI process for disk array product line, evaluated serdes vendors and implemented Fibrechannel technology.

Us

Responsible for high-speed interface design, signal integrity analysis and guidance, PLL fault tolerant clock source module

Houston, Texas, Us

Designer on low skew passive UHF band clock distribution system for mainframe VAX computers