I am a Silicon SOC (or ASIC) design and test engineer with specialization in DFT (Design for Test) with the following highlighted contributions. I am also broadening my skill sets on DV (Design Verification) and Big Data Analytic to handle the latest technology through continuing education and leveraging relevant experiences from past projects.o Delivered high quality ASIC (or SoC) DFT projects on schedule through implementation and verification of Scan, Logic BIST, Memory BIST, JTAG, IO test, and test IPs.o Enhanced the production quality by 30% by developing early test engagement methodology through data analytic and 6 sigma plus techniques.o Developed the DFT methodologies in using various ASIC vendors and the tools of Logic Vision, Mentor, Syntest, Cadence, and Synopsys and managed the projects of 10+ design teams with more than 20 ASIC projects.o Experienced in failure analysis and fault diagnosis by correlating component level (ATE) and system level testing through post silicon debugs addressing the gaps between them. o Cisco certified six sigma plus Green Belt certificate holder.o Project and program management skill with fluent PowerPoint and Excel use.o Teaching DFT and VLSI physical design courses at Santa Clara University.o VLSI design library development experience
Listed skills include Asic, Dft, Silicon, Silicon Validation, and 17 others.