Worked as an RTL designer, tech lead, and first-level manager in Intel’s Advanced Architecture Development Group on a next-gen CPU architecture. Primary implementer for our data prefetchers, plus other cache stuff. Also acted as our chief bug nag and validation liaison.Accomplishments included writing and fixing a lot of RTL, improving code reuse, spearheading bug hunting and code cleanup efforts, implementing X injection, and developing a novel methodology for finding clock gating bugs.Also worked as a cross-box firefighter, leading the design and implementation of our machine check architecture, control register network, L1$ livelock breaker, and other things.I also wrote tools to make designers and debuggers more effective, improve design quality, and improve developer experience.

Architected and implemented a new mid-level cache and coherent fabric for Centaur's next-generation microprocessors. Architected and implemented the DMA engine for our ML accelerator. Developed migration strategy for leveraging legacy blocks in the context of our next-gen processor's memory hierarchy. Developed myriad tools to aid in pre-silicon test debug and code constructs for RTL designers to design safer RTL. Wrote tools to aid in performing gates edits for ECOs, and did the gates edits when the "safer RTL" wasn't safe enough after all.pre-2014: Helped in memory hierarchy design and maintenance, primarily in our LLC. Designed and implemented various mechanisms to aid in post-silicon lab debug and error detection/recovery. Debugged and fixed issues relating to cache coherence, livelocks, deadlocks, starvation, performance, etc. and implemented failsafe mechanisms to diagnose (and recover from) issues found in the lab. Worked to define new simulation checkers for the L2 cache, L1 caches, bus unit, microcode, and core.

Member of x86 pre-silicon functional verification group. Wrote tests and test generators to target specific core units at a core level. Debugged hand-written tests and randomized regression tests. Co-developed and maintained a functional coverage framework for functional testing feedback. Created microcode patch screening procedure to validate experimental microcode patches.Debugged and root-caused bugs across the chip, and proposed fixes in both RTL and Microcode. Created a SystemVerilog-based unit level test environment for testing the L2 cache. Created similar C-based test environment for more aggressive L2 testing in single-core simulation environments.