Dr. Devender Pal Singh Email & Phone Number

Experience in Digital Logic Design, full custom layout, Analog Layout Design, TCAD simulation, CMOS logic design, FinFET based circuit design, SRAM design, Compute-in-memory designKnowlwedge of layout proximity effects Knowledge of Verilog, VHDL, Strong experience in Cadence Virtuoso, Monte-carlo simulation, Routing and placement,Worked on Visual TCAD, Silvaco TCADUnderstanding of Semiconductor Device Physics and CMOS fabrication technology,Understanding of Digital and Analog IC Design,Expert in different validations check such as DRC, LVS, Extraction and other foundry specific validations.Understanding of matching techniques, differential amplifier layout, current mirror layout, SRAM layout, Operational amplifier layout, logic circuits layout