Analysis engineering

Worked in the Reliability Assessment Program. Regularly conducted process health assessments of critical processes within Luminant Generation. These typically included usage of fundamental assessment tools: 1) Surveys; 2) Audits/data mining; 3) Interviews and 4) Direct Site ObservationsDuties required the systematic design of assessment tools, schedules and summary reports for the assessments. Each assessment resulted in a summary presentation to process owners/site management which included the barriers, gaps and best practices. These reports highlighted recommendations for gap closure as well.

Working 20NM low voltage SRAM bitcell yield. Closely interacting with the Memory Solutions design and simulation team to provide the feedback to drive yield.

Yield Analysis Team (2011-2012)▪ Performed product yield analysis including assessment of yield/fail test pareto for devices. ▪ Key contributions to >25% yield recapture on high volume produc, (equivalent to ~ $10,000,000 cost savings. Additional project resulted in ~$1,000,000 cost savings)▪ Conducted statistical analysis of tester and site level dependency to identify setup issues. ▪ Initiated subsequent actions, including PFA, EFA and split lot analysis to resolve issues.Bitcell Characterization Team (2009-2011)▪ Contributed to bitcell design, product development, simulation, and test engineering; ▪ Developed characterization plans. ▪ Assisted transfer of test algorithms between tester platforms▪ Trained test engineers on test structures, expected dataset and analysis to verify implementation▪ Performed simulation and nanoprobe as needed Patent disclosure for modified (higher reliability) bitcell design resulted from work on temperature related bitcell fails.Rapid Ramp Support (2002-2009) . ▪ Supported product ramps, yield issues, and customer returns.▪ Worked with PFA and EFA labs to address flash, sram, and fuse yield issues. ▪ Collaborated with bitcell development team to understand and assess fail bit signatures. ▪ Worked with sram compiler design teams to debug failures▪ Performed bit level dc simulations, e.g., READ , WRITE and SNM, as needed.▪ Performed nanoprobe measurements using Zyvex nanoprobe system to - characterize failing 6T and 1T bitcell probe fails and customer returns. - develop detailed methodology to characterize embedded flash bitcell fails; ▪ Investigated voltage sensitive sram bit fails (soft bits). ▪ Partnered with design and process engineering to investigate and image defects and take corrective actions to contain as well as resolve failures.

Responsibilities included the solar panel design for GPS satellite proposal: size & weight estimates, expected power output, and test module test plan and data analysis.Additional test module construction and testing was also conducted for the DMS Program (DMSP)This required several presentations to USAF personnel during breakout sessions.

Worked under the direction of full professors on vacuum systems and design and implementation of several automation systems.