DSP algorithm design for concurrent multi-band digital predistortion of 4G/5G power amplifiers.Algorithm research for crest factor reduction in Massive MIMO 5G systems.Vectorization of algorithms for massively parallel implementation on Xilinx Versal ACAP devices.Intellectual property generated 9 granted US patents.

DSP algorithm development for 100 and 40 Gbps optical transceivers, including clock recovery, CD/PMD/PDL compensation and adaptation/tracking, and framing synchronization. Intellectual property generated three US patents granted.Architected alternative frequency-domain data path architectures to achieve ~ 50% reduction in gate area over existing schemes.

Architected & led design and development of a large FPGA for WiMAX channelization.Architected large (>1M gate) high performance ASIC blocks for WiMAX and LTE 4G modem & radio signal processing functions. Mentored the execution of the design by a junior engineer during development.Investigated physical layer performance of closed-loop MIMO features of 802.11n using Matlab simulations. Used results to steer WiFi chipset selection and evaluation of vendor roadmaps.Developed FPGA prototype of floating-point matrix inversion hardware for adaptive least squares tracking applications.

Performed digital RTL verification for mixed-signal SERDES chips for 10 Gbps Ethernet PHY applications. Created RTL behavioral models of analog datapath circuits to verify closed-loop system performance across core boundaries.Created system-level models in Matlab and C++ of electronic dispersion cancellation (EDC) algorithms for multi-mode fiber applications. Quantified and optimized overall system performance for various analog circuit implementations and design trade-offs. Algorithmic development resulted in one patent granted.

Investigated optimized architectures and hardware partitionings for 2nd-generation cost-reduced base station channel cards. Architected and implemented a multi-channel high-capacity WCDMA-based path searcher in Xilinx FPGAs. Extended the features & usability of an in-house data capture and test-vector system for laboratory performance testing.

Established, staffed & managed the Ottawa Design Center, a remote field office of the parent company headquartered in San Jose, growing from 1 to 9 employees. Defined & implemented a core project to produce 3G wireless reference designs for the Chameleon reconfigurable platform. Delivered significant marketing collateral to customers including two booth-quality demos, reference designs, app-notes, white papers, and tutorials. Presented product-oriented technical training sessions to customers worldwide.Implemented Verilog-based designs on the Chameleon FPGA platform.Earned “Outstanding Effort Award” and “Technical Achievement Award” for the development of intellectual property resulting in three granted patents.

Developed algorithmic models of a discrete multi-tone ADSL modem and base station channelizer applications. Performed fixed-point analysis, SNR budgeting, and dynamic range optimization for DSP functions including FFT’s, automatic gain control (AGC), and equalization. Created Perl and Matlab scripts for automated ASIC regression testing & verification.Wrote an object-oriented simulator in C++ for the physical layer of the IS-95 cellular standard including convolutional coding, interleaving, channel propagation models, Rake receiver processing, diversity combining, and Viterbi decoding.Received three “Spot Awards” for technical leadership and teamwork.

Conducted research on the application of digital beamforming to future broadband communication satellites employing on-board processing. Performed detailed simulations in both C++ and Matlab to demonstrate performance of algorithms.

Presented a 3rd year undergraduate course entitled "Microprocessor System Principles". Created lab assignments based on Motorola 68HC11 hardware.