Responsible for RTL modeling and simulation of RISC-V-based platforms, as well as the devel-opment and integration of custom peripherals, coprocessors, and accelerators.

Researched and optimized FPGA-based hardware architectures for real-time deep learning tasks,enhancing neural network performance and efficiency, and communicated findings through tech-nical reports and conference presentations.

Automated the process of creating dynamic graphics using JavaScript libraries like Billboard.js.