Ajay Dubey Email & Phone Number

Santa Clara, California, Us

In my role as the Director Of Engineering, AI Networking SoC at Intel Corporation, I provided leadership on AIC Networking Silicon, overseeing projects such as IPUs, Smart NICs, and Network Function Accelerators. Working with cross-functional teams, I defined Landing Zone, MVP, and architecture, ensuring successful HW-FW/SW partition and lab bring up with a diverse team. My experience in both ASIC and FPGA development was crucial in achieving project milestones.

Chaired High Speed Interface Design Track - Discussed next generation Backplane 50Gbps and beyond

Aliso Viejo, Ca, Us

Responsible for developing ASIC component for Actel's high end Flash SoC. Responsibilities included People management, Talent management, Technical leadership to develop Architecture, RTL , DV, and Physical Design. Led the evaluation of third party IPs for the integration of Flash SoCs.

Helped development and customers adaptation of Prism's high speed SerDes solutions

Palo Alto, California, Us

Responsible for digital logic development of 10G PHY products. Contributed to the Micro-architecture, Test plan development, RTL design, BFM & Test bench development, FPGA development, and lab bring-up and silicon validation of 10GB Ethernet PHY chips. Hired, trained, and mentored new members of the team

Santa Clara, California, Us

Led the development of of SONET Framer and OTN/Generic Framing Protocol mapper ASICs. Responsible for delivering MAS , register map, RTL , Verification, Regression, debug, code coverage, synthesis & Timing Analysis, and ECO implementation Owned and developed clusters of complex packet processing blocks from Micro-Architecture to the silicon bring up

Au

ASIC and FPGA design, verification, and Synthesis of customer turnkey projects

Mse, Soc Design

B.Tech, Electronics And Telecommuications Engineering

B.Sc, Computer Science, Physics, And Mathematics

Ph. D. Candidate, Electrical And Electronics Engineering