Ajay Dubey

Ajay Dubey Email and Phone Number

Director Of Engineering, AI Networking Silicon @ Intel | ASIC | FPGA | Platforms & Solutions Engineering @ Intel Corporation
(408) 765-8080
Ajay Dubey's Location
San Francisco Bay Area, United States, United States
About Ajay Dubey

At Intel Corporation, my engineering leadership in AI Networking silicon is underscored by a history of spearheading advancements in High Performance Computing, and networking technologies such as IPUs, Smart NICs, and Network Function Accelerators. With a focus on cross-functional team leadership, we have navigated complex Silicon development, pre-and-post silicon validation, and hardware and firmware integrations to drive successful product launches.My technical acumen in ASIC, FPGA silicon development, and solutions based on them, honed over more than three decade, has been instrumental in defining project architectures and milestones. Our team's collaborative ethos facilitates the lab bring-up process, integrated silicon validation and customer support ensuring Intel's position at the cutting edge of AI and networking solutions.

Ajay Dubey's Current Company Details
Intel Corporation

Intel Corporation

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Director Of Engineering, AI Networking Silicon @ Intel | ASIC | FPGA | Platforms & Solutions Engineering
(408) 765-8080
Website:
intel.com
Employees:
10
Ajay Dubey Work Experience Details
  • Intel Corporation
    Director Of Engineering, Ai Networking Soc
    Intel Corporation Mar 2009 - Present
    Santa Clara, California, Us
    In my role as the Director Of Engineering, AI Networking SoC at Intel Corporation, I provided leadership on AIC Networking Silicon, overseeing projects such as IPUs, Smart NICs, and Network Function Accelerators. Working with cross-functional teams, I defined Landing Zone, MVP, and architecture, ensuring successful HW-FW/SW partition and lab bring up with a diverse team. My experience in both ASIC and FPGA development was crucial in achieving project milestones.
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  • Ethernet Technology Summit
    Chairperson - High Speed Interface Track
    Ethernet Technology Summit 2013 - 2015
    Chaired High Speed Interface Design Track - Discussed next generation Backplane 50Gbps and beyond
  • Microsemi Corporation
    Sr. Manager Silicon Engineering - Flash Soc
    Microsemi Corporation Feb 2008 - Jan 2009
    Aliso Viejo, Ca, Us
    Responsible for developing ASIC component for Actel's high end Flash SoC. Responsibilities included People management, Talent management, Technical leadership to develop Architecture, RTL , DV, and Physical Design. Led the evaluation of third party IPs for the integration of Flash SoCs.
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  • Prism Circuits
    Senior Consultant, Application And Design Engineering Management
    Prism Circuits Jan 2009 - 2009
    Helped development and customers adaptation of Prism's high speed SerDes solutions
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  • Broadcom Inc.
    Digital Design & Verification Lead 10G Ethernet Phy
    Broadcom Inc. 2006 - 2008
    Palo Alto, California, Us
    Responsible for digital logic development of 10G PHY products. Contributed to the Micro-architecture, Test plan development, RTL design, BFM & Test bench development, FPGA development, and lab bring-up and silicon validation of 10GB Ethernet PHY chips. Hired, trained, and mentored new members of the team
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  • Intel Corporation
    Asic Cluster Lead -10Gbps Networking Asics
    Intel Corporation Jul 2000 - Oct 2006
    Santa Clara, California, Us
    Led the development of of SONET Framer and OTN/Generic Framing Protocol mapper ASICs. Responsible for delivering MAS , register map, RTL , Verification, Regression, debug, code coverage, synthesis & Timing Analysis, and ECO implementation Owned and developed clusters of complex packet processing blocks from Micro-Architecture to the silicon bring up
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  • Miscellaneous
    Asic / Hardware Design Engineer
    Miscellaneous Sep 1994 - Aug 2000
    Au
    ASIC and FPGA design, verification, and Synthesis of customer turnkey projects
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Ajay Dubey Skills

Asic Fpga Verilog Soc Ic Altera Functional Verification Modelsim Tcl Logic Design Rtl Design Static Timing Analysis Perl Spyglass Logic Synthesis Serdes Ethernet Vhdl Systemverilog 10g Ethernet Otn Vcs Synopsys Primetime Design Compiler Altera Quartus Xilinx Ise Primetime I2c Quartus Amba Ahb Spi Silicon Hardware Development Pcie Rtl Verification Ncsim Xilinx Ddr Synopsys Tools Interlaken Tk Ethernet Over Sdh Gfp Processors Rtl Coding Debugging System Architecture Hardware Architecture

Ajay Dubey Education Details

  • San José State University
    San José State University
    Soc Design
  • University Of Allahabad
    University Of Allahabad
    Electronics And Telecommuications Engineering
  • University Of Allahabad
    University Of Allahabad
    And Mathematics
  • Indian Institute Of Technology (Banaras Hindu University), Varanasi
    Indian Institute Of Technology (Banaras Hindu University), Varanasi
    Electrical And Electronics Engineering

Frequently Asked Questions about Ajay Dubey

What company does Ajay Dubey work for?

Ajay Dubey works for Intel Corporation

What is Ajay Dubey's role at the current company?

Ajay Dubey's current role is Director Of Engineering, AI Networking Silicon @ Intel | ASIC | FPGA | Platforms & Solutions Engineering.

What schools did Ajay Dubey attend?

Ajay Dubey attended San José State University, University Of Allahabad, University Of Allahabad, Indian Institute Of Technology (Banaras Hindu University), Varanasi.

What skills is Ajay Dubey known for?

Ajay Dubey has skills like Asic, Fpga, Verilog, Soc, Ic, Altera, Functional Verification, Modelsim, Tcl, Logic Design, Rtl Design, Static Timing Analysis.

Who are Ajay Dubey's colleagues?

Ajay Dubey's colleagues are Madhan Mohan, Sharene Ng, Morgan Chandler, Anthony Williams, Geoffrey H., 周巧晴, Prem Kumar Pandey.

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