Responsible for development of Architectural models of Camera Sub Systems for Snapdragon line of SoCs and ensure the IP makes it all the way to silicon by working with Design and Verification engineers, lead a team spread across geographies.Lead a small team of engineers to develop a real time scene classification system running on a mobile phone based on Deep learning which feeds back to Camera stack to improve the image quality, my contribution was an improvement to MobileNets and strategies for dataset construction for optimal scene detection results.

1. Media SoC Memory sub-system: delivered an architecture driven by performance studies, some of the problems addressed were ­how virtual memory design for media sub­-systems would perform, finding suitable candidates for their TLB pre­fetch and replacement policies and analysis of cache sub­-systems suitable for media processing systems.2. Broadcast Receiver development: Architected the framework and developed a system model for a programmable demodulator for Digital TV Broadcast receiver, this was used for performance studies early in the design phase and later as an SDK enabling Software teams to develop a DVB stack to demonstrate feasibility of the whole concept.3. Home networking: Multimedia Over Coax Alliance (MoCA) is an open industry initiative for home networking and specifies MAC and PHY layers along with convergence layers for other standards for interoperability.My role included review of MoCA 2.0 draft specification for Intel standards group, accurate interpretation of the MoCA 1.x specification for hardware and software teams for implementation (this involved hands on lab work with RF networks which lead to a development of home grown sniffer) and also participation in the MoCA alliance Certification Working Group (Standards body) to ensure Intel IP would be ready for certification. On the system and software side, my work involved definition of Firmware layer and performance study of an ARM based FPGA platform to ensure it can successfully execute the MoCA protocol at line rate.

Models for Video post-processing and Display: Hands on technical lead for a team of 6 Engineers working on modeling for Display Processing pipelines and Display controller models for Multimedia SOCs.Responsible for overall software architecture, resource estimates and schedule for development and delivery for our architecture and verification customers.Delivered bit accurate video pipeline models and cycle accurate display controllers for HD video for Media SOCs, studied system architecture tradeoffs for complex media SOCs, several products were introduced in the market which use this work.

Team Lead, IXP 2400 NPU SDK Transactor Architecture tools and their development.Developed cycle accurate simulator to model the entire functionality of the IXP2400 NPU.Also developed relevant tools to provide instruction execution latencies for multithreaded processors and also latencies of different subsystems in the NPU, these are critical in tuning a software stack for line rate performance and these tools have been carried forward for several future generations.

Responsible for MP (Multi-processor) Validation of the Itanium Processor and development of required tools and methodologies for a coverage based approach.Developed a Multiprocessor simulation platform environment for pre-silicon validation, this was used as the primary regression environment for validation of MP functionality, internal customers used this to run a small OS, external customers also used this to verify their chipsets designed for the Itanium processor.Developed assembly level tests and various Architecture tools (MP Cache coherency, data consistency, shared bus protocols, etc), checkers (for checking against RTL/Silicon against reference models) and ensured all MP related micro-architectural scenarios were tested via development of necessary coverage metrics.Debugged silicon as part of post-silicon verification efforts, both on silicon testers and hardware systems platforms as a technical lead at various stages of the first and second generation of the Itanium series of processors.

As part of a research team, invented several new algorithms for high speed cycle accurate simulation which were designed to run on a software or hardware implementation. Concepts used range from graph theory, synthesis, logic design and system architecture.

Automation of VHDL System Simulator (VSS) tools for digital simulations in Design Verification Group.