1. Aug 2024 - NowConfigure, Verification, Customer Support, and Bring Up Uniquify DDR IPSupport additional DDR5 feature development for Uniquify DDR IP

1. Jun 2022 - Aug 2022: Trail projectRun and debug PCIe 4.0 ATE tests to verify the IP function.Run and debug PCIe 5.0 ATE tests to verify the IP function.Research on PLL2. Aug 2022 - Jan 2023: Video Processing IPReview, verify, debug, run synthesis and implementation for the CDCCSC (Clock domain crossing and clock skew compensation) block and PWM Dimming block in the IP.Help TOP owner to integrate, and test the two blocks into the top design.Learn to perform CDC Check by using Meridian Tool.3. Sep 2022 - May 2023: VByOne IPUnderstand the VByOne HS Specification.Review, verify, debug the VByOne IP which follows the VByOne HS Specification.Help supervisor answer customer's question for the IP.4. Sep 2022 - July 2024: DDR IPStudy JEDEC DDR and LPDDR specification.Config, run, and debug the regression tests for the DDR IP.Develop and maintain DDR PHY, Controller IPs.Experience with JEDEC spec DDR3/DDR4/DDR5/LPDDR3/LPDDR4.Experience timing constraint for STA and synthesis.Configure, Verification, Bring Up for DDRIP support.Gate level simulation debugging skill.Clock domain crossing analysis and design rule check tools.

Finish the 6-month Logic Design internship at Uniquify:- Learnt to use Linux operation system- Learnt to write Unix script using Cshell/Perl- Learnt to use tools: Lint check, Verdi, Cadence irun (ncv), Synopsys synthesis tool- Completed a small personal project (FRC: Frame rate control) from high-level design, Verilog coding to synthesis- Research about eMMC 5.1 - Verifying PCIe 4.0 Phy IP: config scripts, run testcases, check waveforms, and report- Verifying PCIe 5.0 Phy IP: config scripts, run testcases, check waveforms, and report- Support manager/supervisors/colleagues with other tasks