Mar 2024 - Present
AeroLeads people directory · profile
Durgesh Srivastava Email & Phone Number
CTO, MIPS
at
MIPS
1 work email found
@nvidia.com
2 phones found area 408
LinkedIn matched
✓ Verified Jun 2026
4 data sources
Profile completeness 100%
Who is Durgesh Srivastava? Overview
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Quick answer
Durgesh Srivastava is listed as CTO, MIPS at MIPS, based in Cupertino, California, United States. AeroLeads shows a work email signal at nvidia.com, phone signal with area code 408, and a matched LinkedIn profile for Durgesh Srivastava.
Durgesh Srivastava previously worked as Chief Technology Officer at Mips and Board Member representing NVIDIA at Universal Chiplet Interconnect Express (Ucie). Durgesh Srivastava holds Btech, Electrical Engineering from Indian Institute Of Technology, Kanpur.
Company email context
Email format at MIPS
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{first_initial}{last}@nvidia.com
86% confidence
AeroLeads found 1 current-domain work email signal for Durgesh Srivastava. Compare company email patterns before reaching out.
Profile bio
About Durgesh Srivastava
Technical* Data Center Infrastructure, Disaggregated architecture, Memory Pooling, Accelerator as a Peer, Fabric Management* Linux kernel module for hot-cold pages, Memory Management, Performance profiling, HW-SW co-enabling, Autonomous Driving Data Center* Server SoC architecture, Xeon/Atom SoC architecture, Cache and memory coherency silicon Debug, FPGA prototypingLeadership* Product Requirements, Definition and Execution, Roadmap definition, Bringing order out of chaos, and Coach, and Mentor
Listed skills include Leadership, System On A Chip, Debugging, Integrated Circuits, and 18 others.
Current workplace
Durgesh Srivastava's current company
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8 roles
Durgesh Srivastava work experience
A career timeline built from the work history available for this profile.
Board Member Representing Nvidia
Jun 2022 - Mar 2024
Data Center Product Architect And Senior Director
Working on next generation Data Center SoC and Systems Innovation
Jun 2021 - Mar 2024
Data Center Infrastructure Systems Architect And Senior Principal Engineer
Cloud And Automotive Infrastructure Team, Intel Corp
- Desegregation architecture for CPU, Accelerators, Memory, and Storage
- Memory Pooling and Extension: Developed a fully functional prototype for SW/HW solution for coherent memory. Used various memory access patterns for cloud usages for workloads, detecting Cache-line patterns as well as.
- Linux Kernel Module: Developed a module that detects hot-cold pages and moves pages to improve performance
- Memory Pooling Fabric architecture: Developed for scale up of the memory by connecting it to 40+ nodes in a rack and across racks. A functional prototype is fully functional with FPGA and Kernel Modules/Patches.
Nov 2018 - Jun 2021
Cloud Infrastructure Architect For Autonomous Driving And Senior Principal Engineer
Automotive Solutions Division, Intel Corp
- Automotive cloud: Founded and led the Automotive cloud team (SWE, Platform Engineers, Program Managers, and Customer Engineering), delivered a Hadoop based big data platform to store and process data generated from.
- Product Execution: Deployed the solution for 20-25 cars at BMW and Renault to manage, store and process 5 TB/hour data from a car. Created a roadmap to manage full scaling of the fleet from 2-3 cars to 150 in various.
- Product Deployment: Solution provided a full working environment for the data scientists, simulation engineers, and system integrators with quick access to data with hybrid cloud with batch jobs bursting into private.
May 2016 - Nov 2018
Platform And Software Lead Architect - Intel In-Vehicle Infotainment Solution
Embedded And Iot Division, Intel Corp
- Product Architecture, Execution, and Deployment: Initiated and formed a 20-person team to bring open-source kernel & middleware to Toyota’s infotainment strategy. The primary objective was to bring Android’s middleware.
Nov 2010 - May 2016
Chief Architect And Product Engineer
Cpu, Soc And Chipset, Intel Corp
- Lead silicon architect for Atom-based SoC for Automotive and low-power laptops/tablets. Key highlights and changes were related to memory controllers, graphics, Blu-ray, display unit, Intel legacy block, and PCI-E
Jan 2005 - Nov 2010
Systems And Silicon Architect
Xeon And Itanium Architecture, Intel Corp
- Silicon Architecture and Execution: defined and delivered 5 revenue generating silicon products
- DDR2-RDIMM based Xeon chipset for reduced power
- Expertise on Itanium and Xeon cache coherency and Debug hooks architecture.
Jan 1997 - Oct 2005
3 education records
Durgesh Srivastava education
Btech, Electrical Engineering
Indian Institute Of Technology, Kanpur
Mphil, Electronics Enngineering
The Hong Kong University Of Science And Technology
Education record
Kendriya Vidyalaya
FAQ
Frequently asked questions about Durgesh Srivastava
Quick answers generated from the profile data available on this page.
What company does Durgesh Srivastava work for?
Durgesh Srivastava works for MIPS.
What is Durgesh Srivastava's role at MIPS?
Durgesh Srivastava is listed as CTO, MIPS at MIPS.
What is Durgesh Srivastava's email address?
AeroLeads has found 1 work email signal at @nvidia.com for Durgesh Srivastava at MIPS.
What is Durgesh Srivastava's phone number?
AeroLeads has found 2 phone signal(s) with area code 408 for Durgesh Srivastava at MIPS.
Where is Durgesh Srivastava based?
Durgesh Srivastava is based in Cupertino, California, United States while working with MIPS.
What companies has Durgesh Srivastava worked for?
Durgesh Srivastava has worked for Mips, Universal Chiplet Interconnect Express (Ucie), Nvidia, Cloud And Automotive Infrastructure Team, Intel Corp, and Automotive Solutions Division, Intel Corp.
How can I contact Durgesh Srivastava?
You can use AeroLeads to view verified contact signals for Durgesh Srivastava at MIPS, including work email, phone, and LinkedIn data when available.
What schools did Durgesh Srivastava attend?
Durgesh Srivastava holds Btech, Electrical Engineering from Indian Institute Of Technology, Kanpur.
What skills is Durgesh Srivastava known for?
Durgesh Srivastava is listed with skills including Leadership, System On A Chip, Debugging, Integrated Circuits, Big Big Data Analytics, Processors, Asic, and Team Leadership.
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