Driving Data Center Technical Strategy for MIPS-RISCV

Working on next generation Data Center SoC and Systems Innovation

Desegregation architecture for CPU, Accelerators, Memory, and Storage• Memory Pooling and Extension: Developed a fully functional prototype for SW/HW solution for coherent memory. Used various memory access patterns for cloud usages for workloads, detecting Cache-line patterns as well as hotness of the page using Page Tables Accesses and migrating pages. Integrated some of the static and compile-time attributes for better locality• Linux Kernel Module: Developed a module that detects hot-cold pages and moves pages to improve performance• Memory Pooling Fabric architecture: Developed for scale up of the memory by connecting it to 40+ nodes in a rack and across racks. A functional prototype is fully functional with FPGA and Kernel Modules/Patches.

• Automotive cloud: Founded and led the Automotive cloud team (SWE, Platform Engineers, Program Managers, and Customer Engineering), delivered a Hadoop based big data platform to store and process data generated from Autonomous vehicles• Product Execution: Deployed the solution for 20-25 cars at BMW and Renault to manage, store and process 5 TB/hour data from a car. Created a roadmap to manage full scaling of the fleet from 2-3 cars to 150 in various geographies. • Product Deployment: Solution provided a full working environment for the data scientists, simulation engineers, and system integrators with quick access to data with hybrid cloud with batch jobs bursting into private cloud

• Product Architecture, Execution, and Deployment: Initiated and formed a 20-person team to bring open-source kernel & middleware to Toyota’s infotainment strategy. The primary objective was to bring Android’s middleware for faster innovation and reducing the development cost. Used the solution to lead Land Rover’s infotainment design using MeeGo/Tizen middleware. Intel Infotainment solution is now deployed with 5 car manufacturers

• Lead silicon architect for Atom-based SoC for Automotive and low-power laptops/tablets. Key highlights and changes were related to memory controllers, graphics, Blu-ray, display unit, Intel legacy block, and PCI-E

• Silicon Architecture and Execution: defined and delivered 5 revenue generating silicon products• DDR2-RDIMM based Xeon chipset for reduced power• Expertise on Itanium and Xeon cache coherency and Debug hooks architecture.