Dwight Patterson Email and Phone Number

• Senior Principal SoC/FPGA/ASIC Design/Verification Engineer on multiple SoC/IP core projects and EngTech Services programs.• Responsible for project schedule, resources, specification, design development, verification, and documentation of IP modules.• Team leader on low-power, multicore designs that include DSP cores, I2C, SerDes, and FSMs.• EDA tool flow expert (Synopsys, Cadence, Mentor Graphics) for ASIC and FPGA: Verilog/VHDL RTL, SDC design constraints, synthesis, testbench creation, simulation, STA, and place and route.• Senior contributor on a new SoC Cores engineering effort in the analog sensor space, investigating power efficiency for low-power applications.• Group leader of the SoC Cores Evaluation Group that investigates IP cores using performance, low-power and design area criteria.• Created documentation of core specifications for design development, verification, and re-use.• Recently completed assignment with Texas Instruments on 3 mixed-signal SoCs for high power drivers (APP – HVP – HPD) in the automotive industry (functional safety): Performed RTL design, SDC synthesis, DFT SCAN and ATPG, linting, digital verification (System Verilog bit-exact simulations), and STA under constrained, aggressive schedules.• Dwight Patterson's quote: "Engineering is applied math and science to solve real world problems!"

UVM Verification Engineer – Cirrus Logic - Randstad Technologies Contractor• ASIC UVM System Verilog verification engineer on a mixed-signal, next generation audio chip.• Created UVM reusable virtual sequences and randomized tests to verify the correct functionality of the digital I/F.• Constructed a simulation checker to find errors and useful warnings for test runs in Cadence's Incisive simulator.

Senior Verification Engineer - Texas Instruments - High Performance Analog - Audio Imaging Products Group• Lead ASIC verification engineer on a digital front-end/analog back-end, audio waveform generator, mixed-signal chip. This device was a FIRST PASS SILICON SUCCESS!• Developed self-checking System Verilog testbenches, ran simulations in NCSim examined waveforms in Synopsys Verdi Automated Debug Program, and setup a complete regression simulation environment.• Utilized Cadence’s Incisive Metrics Center (IMC) for verification code coverage.• After the audio waveform generator device PG’ed, I was re-assigned to create an 8-channel, 32-bits per channel TDM Receiver (TDM serial input, with multi-channel, 32-bits per channel, parallel outputs) in Verilog RTL and the SystemVerilog, self-checking testbench environment to verify the functionality.

• VHDL RTL FPGA Design Engineer on Lockheed Martin's NuPAC project.• Investigated and debugged the FPGA core design functional defects while interfacing with a UVM verification team.• Core design had over 40 FSMs for various control blocks. Created safe state encoding for all FSMs.• Documented FSM details and project design reports for version releases.• Created “FPGA Checker” linux utility for checking various FPGA design details, tool errors, and warnings.

• Digital and analog design/verification engineering with focus on chip level design.• Managed electrical engineering laboratory work, with intensive Multi-Sim (Pspice-like) analog/digital simulations.• Produced weekly technical presentation material (content creation) for engineering instruction.

• Documented and designed Verilog RTL with DFT components for digital VCO calibration and programmable clock dividers for high-speed mixed-signal chips running up to 1.2 GHz. This device was a FIRST PASS SILICON SUCCESS!• Synthesized design with DFT SCAN chains using Synopsys DC and Cadence RC with SDC timing constraints using TI ASIC libraries. Fixed all SCAN problems in RTL for high SCAN coverage.• Created an unique and successful EDA synthesis methodology to increase digital netlist clock speeds from MHz to GHz for greater design performance.• High-quality netlist hand-off to the back-end team for very efficient, low-human-effort place and route layout.• Ran Spyglass for RTL linting and created an ASIC Checker utility for Synopsys design examination.• Verified RTL and gate-level netlists using Cadence NCSim and back-annotated SDF with created Verilog self-checking testbenches.• Supported the back-end team and performed post-layout static timing analysis with SDC and SDF (min, typ, max) in PrimeTime.• Oversaw layout and clock tree analysis.• Netlist hand-off to client and provided customer support for the design use.• Interfaced with analog engineers to develop mixed-signal RFICs.

• Designed digital ADC, filter, mixer, and angle of arrival components for a low band digital filter receiver.• Created Verilog RTL for Xilinx Virtex 6 FPGA implementation.• Utilized Xilinx CoreGen for DDS (Direct Digital Synthesizers) for sine/cosine NCO (numerically controlled oscillator) Verilog code generation.• Hand instantiated Xilinx Virtex-6 FPGA DSP48E1 core into Verilog RTL modules for high speed (approaching 600 MHz) mathematical functions.• Developed Verilog testbenches for each RTL module along with design specification documentation.• Used QuestaSim and Matlab for verification simulations.• Ran place and route in Xilinx ISE.

• Developed the ASIC/FPGA tool flow for Samsung's Wireless Systems Lab HW Digital Engineering organization, using Synopsys Design Compiler-Ultra, DFT-Compiler, Power-Compiler, PrimeTime, Xilinx, and Mentor Graphics’ FormalPro for 65nm and 90nm technology on LINUX/UNIX platform.• Designed Verilog RTL for DSP and mathematical blocks for ASIC and FPGA devices.• Generated synthesis, power, DFT for SCAN, and static timing analysis constraints for individual Verilog RTL blocks and for the top-level core which were used by DC, DFT-C, Power-C, and PT.• Created an ASIC checker utility for fast feedback to designers and technical management on the status of Synopsys synthesized netlists so that the design team can make more informed decisions about their RTL architecture early in the design process and for documentation.• Constructed Verilog testbenches for individual RTL modules and ran simulation in ModelSim. • Back-end interface with the ASIC vendor.• Mentored and guided ASIC/FPGA engineers on front-end design tasks and back-end interface duties.

• Project manager and team lead of a design group that supported multiple on-site and off-site customers with their ASIC, FPGA, and SoC IP core integration design projects.• Project management: created and directed project schedule, staff resources, and managed program issues.• Technical pre-sales interface and post-sales support of company customers.• VHDL and Verilog RTL design, synthesis, testbench creation, simulation, static timing analysis, and backend place & route for consumer products.• Video MPEG-2 FPGA design project work.• Created and led client presentations and demonstrations in small and large group settings.• Technical pre-sales interface and post-sales support of company customers.

• Lead designer on the UTOPIA-2 (IP01) project. This device was a FIRST PASS SILICON SUCCESS!• Verilog RTL design to synthesis for ASIC and FPGA implementations using Synopsys Design Compiler and Xilinx XST.• Instructed junior designers concerning ASIC and FPGA design engineering tasks.• SCAN insertion during synthesis using Synopsys Design Compiler and Test Compiler.• Ran ATPG using Synopsys TetraMax to create SCAN vectors.• Created a Synopsys ASIC checker to find post-synthesis design problems early in the flow.• Verilog testbench creation for verification effort.• RTL, SureCov (code-coverage), and gate-level simulations with worst, typical, and best case SDF using Verilog-XL and NC-Verilog simulators and Signalscan for waveform viewing.• Performed SureCov analysis to examine entire verification test suite for uncovered portions of the design, with the goal of 100% block coverage.• Placed and routed designs in Xilinx FPGAs for design emulation before ASIC silicon.• FPGA to ASIC migration on 3 telecom projects.• Created layout floorplans for various designs.• Interfaced with layout team by providing post-synthesis netlist, timing constraints for timing-driven place and route, clock tree generation constraints, design floorplan, and critical path information.• Ran static timing analysis with SDF (worst, typical, and best) using Synopsys PrimeTime.• Performed post-layout synthesis reoptimization using Synopsys Floorplan Manager with the post-route PDEF, SDF, and "set_load" capacitance/resistance information.• Ran formal verification using Synopsys Formality.• Lab tested ASIC and FPGA devices using various lab test equipment.

• Implementation team lead for latest PCI digital device.• Performed IDS10K failure analysis on ASIC chips.• Executed Synopsys Floorplan Manager reoptimization using PDEF, SDF, and net capacitance information. • Performed TI cost analysis on a series of new ASICs.• Wrote tool scripts for Synopsys synthesis.• Performed RTL and post-layout SDF simulations using ModelSim, Verilog-XL, and Signalscan.• Created static timing analysis scripts for Synopsys PrimeTime.

Design Engineer on the HSIS project• Lead ASIC designer for the bus interface chip on the HSIS project• Wrote VHDL RTL for the ASIC design• Synthesized the RTL using Synopsys Design Compiler.Performed RTL and gate-level simulations using ViewSim.• Inserted SCAN using Synopsys Test Compiler.Design Engineer on the ATM project• Responsible for support on 5 ATM ASICs.• Synthesized VHDL RTL using Synopsys Design Compiler.• Inserted SCAN and ran ATPG using Synopsys Test Compiler.• Fixed timing violations in Compass layout, Synopsys synthesis, and VHDL RTL.• Created various Synopsys utilities for more efficient ASIC design flow, including an ASIC design checker and an in-place reoptimization tool.Design Engineer on the ATMC project• Responsible for verification of the Motorola ATMC ASIC.• Created VDHL tests for mixed VHDL, Verilog, and LMC model simulations using ViewLogic's Fusion simulator.• ATMC ASIC was a first-pass silicon success.Design Engineer on the OC-3 SONET project:• Designed 4 Xilinx and 1Altera FPGAs in VHDL for datapath control for the OC-3 SONET platform.• Used Synopsys Design Compiler for synthesis.• Placed and routed the designs using Xilinx and Altera backend tools.• Performed RTL and back-annotated gate-level simulations using Mentor Quick-HDL.• Ran static timing analysis using Synopsys DesignTime and Xilinx tools.• Programmed FPGAs (EEPROM) in the lab tested all devices during integration on the platform.• Applied and received a patent for this design -patent #6,044,088• Design Engineer on the Next Generation Signaling Server project:• Developed VHDL testbench for RTL simulations of a PCI device.• Created PCI protocol procedures in VHDL for reuse on multiple designs.• Design Engineer on the S12 projectDesigned 4 Xilinx FPGAs in VHDL RTL to perform datapath control.• Synthesized VHDL using Synopsys Design Compiler.• Placed and routed the designs using Xilinx backend tools.• Static timing analysis using Synopsys and Xilinx.

Also known as Alcatel-LucentSee Alcatel-Lucent for design responsibilities and experience

Design Engineer on the P516 program:• Responsible for 3 LSI Logic ASICs.• Created VHDL RTL to implement over 30 DSP and ALU functions.• Simulated RTL using Vantage VHDL simulator.• Synthesized ASICs using Synopsys Design Compiler.• Verified gate-level functionality by accelerated simulations using IKOS and stimulus/result vectors generated from the C-language system-level testbench.• All 3 ASICs were first-pass silicon successes.• Obtained D.O.D. secret clearance in early 1992.Design Engineer on the MM-F16 program:• Responsible for 2 TI ASICs.• Synthesized ASICs using Synopsys Design Compiler.• Performed RTL and gate-level simulations using ModelSim and ZYCAD.• Inserted CBIST SCAN throughout the chips.• Ran static timing analysis using TI internal tools.Design Engineer for the TI DSEG CAE group:• Designed VHDL behavioral models of various chips for board-level simulations

• Responsible for digital design, electrical engineering instruction to college students.• Taught many sections per semester of sophomore and junior level EE students.• Designed digital lab experiments for classroom instruction and demonstration of engineering theory.• Utilized VHDL, simulation, synthesis, and backend tools for various programmable devices.