Esosa Amayo Email and Phone Number

• Driving architectural decisions pertaining to the selection of data stores and associated technology stack.• Developing all aspects of predictive modeling pipelines for classification and regression tasks.• Evaluating feature selection algorithms in the machine learning literature for fast, low-complexity strategies for feature elimination in order to scale up the models being developed.• Evaluating open-source tools as components of our workflow for rapid prototyping of the learning algorithms underlying the analytics platform

• Part of a small team of Application-specific integrated circuit (ASIC) designers and Digital Signal Processing (DSP) engineers that developed 1 Gbps burst-mode transmission chipset for home networking over powerline.• Lead and/or primary contributor in the development of various powerline modem firmware modules such as network topology management, secure network communications functionality and neighbor network coexistence functionality.• Implemented a standard-compliant burst mode transmission pipeline while working around glitches injected by 3rd party analog front-end.• Provided requirements and algorithmic guidance to our ASIC team during the design phase of our large-integer arithmetic accelerator IP core.

• Part of a small team of ASIC and DSP engineers that brought xDSL central office 100/24/12 Mbps chipset to market.• Sole contributor and architect in the development of various modem features such as double-ended line testing diagnostic operation mode and power management functionality.• Developed optimization approaches for automatically configuring ASIC cores. In particular, developed constrained-optimization approach for configuring interleaver/framer/coder accelerator cores.• Developed solutions for robustly detecting various training and showtime signals.• Implemented fixed-point utility math functions needed by various firmware modules.