Summer Internship
During my internship at Intel Unnati Training, I worked on developing slow and fast algorithms within a Finite State Machine (FSM) framework, using Verilog HDL. The project aimed to design and implement these FSMs on an FPGA using the Intel Quartus Prime Lite platform. I wrote Verilog code to describe the FSMs, ensuring accurate state transitions and efficient logic design. Using Quartus Prime Lite, I synthesized and simulated the designs to verify their functionality and performance. This experience provided me with hands-on skills in FPGA design, digital logic, and the practical application of computer architecture principles. It also enhanced my understanding of the trade-offs involved in hardware design and optimization.