Evan Pearson Email & Phone Number

Boise, Idaho, United States

Leading a technical team focused on uptime improvements and reduction of DRAM faults in server applications, especially cloud service providers. Managing tens of millions of DRAM data points from customer telemetry data, driving improvements and novel system solutions for improved system performance and improved DRAM quality metrics.

Taichung, Taiwan

--Leading Taichung, Taiwan team of up to 16 engineers for DRAM (DDR5, DDR4) silicon design readiness and validation team--Debug of critical silicon design issues to enable ES, QS and Qual Release to enable shipment to customers--Close work with DRAM design, validation, and yield teams to enable full spec compliance and internal and customer validation success

Taichung City, Taichung City, Taiwan

--On expat assignment for Micron Memory Taiwan, leading product debug and yield ramp for a leading edge DRAM node (1-alpha) from new product introduction (NPI) through qualification and ramp to mature yield--Led a team of 6 engineers from first silicon validation through customer samples, qualifications and product volume ramp--Led debug of critical quality and yield issues quickly through cross functional teams to protect customer quality and revenue

Boise, Idaho, United States

--Responsible for driving a large, cross-functional team to ensure best in class data eye and signaling performance for DRAM products (DDR4, DDR5, etc)--Signal Integrity (SI), Module Design, Systems Compatibility, DRAM design, Test Engineering and Business Unit requirements are all critical to IO signaling performance--Data eye characterization across multiple platforms (component and module ATE, Intel systems RMT, AMD systems Memeye)

Boise, Idaho

--Drove validation debug efforts of Micron's first 3DS DDR4 leading to a successful on-time internal and customer qualification--Lead author of a technical paper regarding novel electrical yield improvement techniques used to drive mature electrical yield for 3DS DDR4--Wrote and maintained python scripts for automated, large-scale analysis of test yields to identify yield improvement opportunities--Deep experience with cross-functional and global engineering teams--Expert in high-speed datapath circuitry and debug, with deep knowledge of 3DS-specific datapath innovations--Experience with large-scale yield analysis and electrical characterization analysis in JMP--Completed debug and applied corrective action for electrical and mechanical device failures across many DRAM technologies (DDR4 3DS, monolithic DDR4, LPDDR4, DDR3, DDR2)--Developed and debugged DRAM test patterns for several test platforms (Advantest 5511, 5501, and 5592 and well as Micron's in-house Mongoose and Micromate platforms)--Drove RMAs to appropriate corrective action using logic analyzer captures of fails and converting failing pattern to test code--Simulated full chip and block-level circuits using Verilog, Finesim and HSpice to correlate to electrical failure data--Experienced in design-for-test (DFT) modes design and operation--Debug of high priority RMAs for critical DRAM customer qualifications --Debug and resolution of validation and qualification device failures

Bozeman, Mt

Tested emerging software technologies, brainstormed potential industry use-cases and worked with industry leaders to determine mutually beneficial patent license agreements.