Eda Tuncel Email & Phone Number

• Member of a small team developing an in-house software package enabling process and hardware engineers to easily access tool data and metrology. This resulted in time savings for the analysis of data collected during.
• Provided training for engineers in order to proliferate the product and improve its usability through feedback

Santa Clara

• As member of a team supporting global semiconductor equipment manufacturing services across product lines ranging from software to hardware, enabled the use of FDC to improve service offerings and market share. In.
• Enabled the collection and visualization of data by merging tool build and field install data to reduce tool start up time and increase the efficiency of chamber matching across two fabs and 15 tools.
• Product Line Management for the Etch service business unit: participated in the release of new etch products

Advanced Energy Products Division

• Participated in the design optimization of an epitaxial chamber for GaN growth through four modeling and characterization cycles within six months. Process performance feedback was used by hardware engineers for.
• Effectively used JMP for minimizing number of experiments, performing data analysis and providing predictions for film thickness non-uniformity and surface morphology improvements.
• Implemented monitoring of chamber hardware parameters through SPC to measure, then predict maintenance cycle times and characterize process drift, thus improving production worthiness of chamber.
• Participated in the accelerated development over a period of six months and the 100 run qualification of plasma cleaning for nGaN MOCVD chamber. Process/clean cycle times reduced by up to 30% and lower cost of.

Etch Division

• Participated in the process characterization of hardware improvements to poly etchers used for double patterned amorphous carbon hardmask transfer in STI and gate applications. Through additional process tuning.
• Performed demonstrations on Applied Materials 300mm dielectric etchers for qualification at 5x/ 4x DRAM nodes. Traveled to provide on site support for start-ups and process tuning for POR oxide etchers’.
• In order to reduce delays in data collection and accelerate demo turn around time, set-up CD SEM measurement recipes on multiple tools. Careful, detailed data collection, including SEM pictures, and clear presentations.
• Active in process characterization aspect of hardware CIP programs of etchers, including extended 2mm edge exclusion CD, plasma uniformity related line width and trench depth non-uniformity improvements.
• Increased customer satisfaction through frequent conference calls that included report preparation and data presentation.

Developed front and back end oxide etch processes for 0.12um Flash memory. Developed and characterized Oxide Hard Mask etching for 193nm patterned line/space features with reduced line edge roughness.Developed contact etching for 193nm patterned holes (AR 5:1).Implemented changes to contact etching of 0.18um generation devices that resulted in WET yield.

Performed demonstrations on Applied Materials 200mm and 300mm dielectric etchers. Performed demonstrations in Contact, Via, DTMO, Dual Damascene Via and Trench, PCMO, Nitride Hard Mask Open etching that resulted in tool sales.Improved significantly demonstration turn-around time and assured in-depth characterization of etch processes by programming and.

Set-up a spectroscopic ellipsometer to measure film thicknesses, optical constants of thin films (ferromagnetic alloys XMnSb) and bulk materials (LiNbO3 ). Measured surface/interface morphologies in GaN/Al2O3 using spectrocospic ellipsometry and AFM.

Bsc, Physics

Doctor Of Philosophy (Phd), Physics

Master Of Science (Msc), Physics