Edith Mateo Email & Phone Number

Los Angeles, California, United States

‘Navitas develops ultra-efficient gallium nitride (GaN) semiconductors that are revolutionizing the world of power electronics in terms of efficiency, performance, size, cost and sustainability.’ Let’s go GaNFast!

Mobile SolutionsDirectly interface with IC design engineers in US and Singapore to convert circuit designs into cost effective integrated circuit products for use in Radio Frequency (RF) and mobile communications systems. Its products include power amplifiers, front-end modules and RF products for handsets and wireless infrastructure equipment. • Full custom chip floor planning, top level, block making, std IP cells, and integration of complex high-performance ICs with RF, analog, and mixed-signal process.• Full layout verifications using Calibre: DRC/LVS/ANT/ANT_MIM/Density/LUP/ERC• Led different IC’s including LNA, CMOS, ASM from different sites in Irvine, Cedar Rapids, San Jose, Newbury Park, and Singapore. • Responsible to get the job done and to ensure we are meeting the project schedule and delivering high-quality in RF, analog, and mixed signal process.• Mentored new hires and other layout engineers in optimizing size and performance of layouts, and imparted effective approach in debugging verification errors to enhanced work efficiency and teamwork.• Created ‘Density Calculator’ for layout and design teams to calculate the width of metallization to use to meet current density target and very useful to trace width calculations.• Created a detailed ‘Layout Tape out Release and Archiving’ cross-functional checklist. • Created training materials beneficial for the layout team.• Performed project tape out process to foundries.• Involved in interviewing and evaluating process of potential layout team members.

El Segundo, California

High Voltage IC'sDirectly interface with IC design engineers in US, Italy, and Austria to convert circuit designs into cost effective integrated circuit products. Executed design tape-outs. • Received award for achievement of enabling products manufactured with specific technology to meet and exceed ruggedness while maintaining density benefits. • Performed chip floorplan, PWR / GND routing, block level routing and top level integration with I/O ESD pad structures.• Performed Analog/RF and Digital blocks such as Receivers, PLL, Amplifiers, References, , Comparators, Voltage Regulators, Drivers, A/D converters, Bandgap, Oscillator, UVLO, OTP, OVP, OCP, PFC, VCO, Thermal Shutdown, Bias, Sense, MOT, PWM, Dead time, I / O ESD cells, Pre-driver, Output Driver, Level shifter, Charge Pump, Dimming Control, Logic Control, Restart logic, Fault logic, Pulse gen, Protection logic, Serial blocks, Clock gen, Read gen, Data Ready, Power Mux, Timer, etc. • Performed 1 chip layout design for Energy Saving Applications technology from analog, digital, and mixed-signal ICs. Key products are for Appliances, Lighting, Display, Audio, Automotive, SMPS, and Industrial Power Control. Typical applications are for: General Purpose Gate Driver, DC-DC converters, Plasma display panel (PDP) applications, LCD, Telecom SMPS, AC-DC adapters, ATX SMPS, Server SMPS, LED Drivers, Charger, AC-DC adapters, Appliance motor drives, Servo drives, Micro inverter drives, Programmable Frequency Control, Home theater systems, Powered speaker systems, Home audio systems, General purpose audio power amplifiers, Dimming Ballast Control, etc.• Performed layout verifications • Prepared packaging technical drawings / bonding die drawing reports for device testing.• Assisted others in optimizing size and performance of layouts, and imparted effective approach in debugging verification errors to enhanced work efficiency and teamwork.

Directly interfaced with IC design engineers in US and Singapore to convert circuit designs into a cost effective integrated circuit products. • Performed challenging IC Mask Design of advanced analog and mixed signal ICs with Singapore and U.S. Design Engineers.• Participated in technical layout / design reviews. • Responsible for the whole layout until tape-out. • Delivered excellence to every layout. Resulted in transfer to parent company in US.

Layout Staff (Senior Block Design Engineer and Floor Planner certified)Performed full-custom analog, digital, and mixed-signal of cells, blocks, and top-block layout.A fast paced workplace, very limited time to study new process required for the project given a tight schedule. With work's efficiency is highly expected, my layout skills had been molded achieving high standard and quality layout in every project done.• Layout schedule estimation. • Layout cells, blocks, and floor plan for top blocks.• Performed data verification using Dracula DRC, DSC, LVS, ERC, grid-check and by manual checking. • Oversaw quality check for block design done by trainees and new employees.