Senior Layout Engineer
Current- Extensive experience in handling DIO library creation in various process node (TSMC/GF/IFS)- Participated and subsequently in charge of testkey development.- Perform all physical & reliability verification (DRC/LVS/ERC/etc.) on the layout designs and ensure the database is fully compliant with all requirements of tape-out flow.- Work closely with circuit design engineers to drive physical implementation and achieve necessary requirement and quality.- Collaborate closely with other colleague various sites across company. Lead and mentor junior to produce the good quality layout and deliver within the given time frame.