Nathan Skinner Email & Phone Number

San Jose, Ca, Us

SoC IP designer and owner for various IP blocks over the years. Currently, ASIC design lead for custom multicore DSP processors. Previous ownership includes data path, data path protections and high-speed serial interfaces. Consistently deliver excellent results on time with aggressive schedules on multiple projects, often simultaneously. Successfully launched multiple SoCs into silicon, provided post silicon support. In addition to IP design, experienced in verification and testbench environment development (UVM). Work includes creating new UVM sequences, tests, scoreboards, register prediction and checking.Responsible for developing and supporting SoC based IP: • Scoping new features (design effort estimates)• Writing micro-architecture specifications for FW, Verification and other HW designer consumption• Implementing RTL (System Verilog)• Designing for low power, clock gating and recovery• Performing lint checking, warning evaluation and correction • Developing metal ECO’s via netlist manipulation • Evaluating CDC’s (clock domain crossings), implementing appropriate synchronization across clock domains• Timing closure and STA on physical design• Closing Code Coverage (FSM, Block and Expression)• Supporting Verification and FW efforts• Providing prototyping platform support (FPGA, Prodium, Palladium)• Experience designing HW for AMBA AXI, AHB and APB protocols

San Jose, Ca, Us

Responsible for developing and supporting SoC based FPGA prototypes on Dini dual Xilinx Virtex 6 and single Virtex 7 platforms. Created and replaced SoC vendor IP PHYs (DDR3, SETM, SATA, SAS), PLLs/Clocks and I/O with Xilinx IP. Partitioned SoC across multiple FPGAs. Serialized AHB, APB buses, interrupts and various other signals to reduce I/O count between FPGAs using SerDes. Worked on all aspects of FPGA development: simulations, synthesis, place and route and timing closure. Translated SoC and created timing constraints for Multi-cycle Paths (MCP), clocks and false paths.Worked on all aspects of FPGA development:• Simulation• Synthesis • P&R (place and route)• Timing closure techniques (Pipelining, Timing Constraints {MCP, clocks, false paths})• Lab bring-up• Instrumented designs for debug

Rueil Malmaison, Paris, Fr

Hardware (HW) and Firmware (FW) design roles developing control boards to be used in multiple PV (Photo Voltaic) products (100kw – 630kw inverters).Firmware design work included:• FW design lead• TI DSP FW architecture• Implemented large portions of control board FW• Inverter current and voltage regulators• I2C driver for temp sensor• SPI drive for EEPROM• Many other features and functions• Designed digital filters with Matlab and implemented in CHardware design work included:• FPGA• HW fault detection• SPI interface to EPROM• Power bridge, DAC, ADC, CPLD interfaces• TI EMIF interface to DSP processor• CPLD• Designed watchdog timers to monitor multiple processors• Reset circuitry and board voltage source sequencing• Control board design (component selection, schematics and analog simulations)• Analog filter design (bandpass, anti-aliasing, power conditioning)• Board bring-up

Designed and implemented engineering test hardware and firmware for Mixed Signal ASICs used for MEMS devices. This included the schematic design and component selection of test and control boards. Designs used in both lab and manufacturing environments. Test boards designed to withstand extreme temperature conditions, -40°C to 125°C temperature cycling.Hardware design work included:• Digital interface debugging and usage of SPI, CAN, RS-232• Debugged and validated designs with: Oscilloscopes, Logic Analyzer, DSA, Signal Generator, DMM• Data and statistical analysis used to develop product specifications• Analog design and simulation Cadence (PSpice)• Schematic capture of design done in Mentor Graphics PADS

Msee, Asic Design

Bsee, Electrical Engineering