Ed Maxwell Email & Phone Number

Santa Clara, California

- Engineer for SPARC (UltraSPARC III+, IV, IV+, T1, T2, T3, T4, T5, M5, M6, M7).- Lead Debug Engineer for all CPUs failing at system manufacturing and at external customers.- Performed correlation work between the chip tester and the system to establish appropriate guardbands for the manufacturing production test program.- Worked with the external fab vendor to make process improvements (CMOS), enhance tester coverage, and increase test yields.- Worked with Design Engineering on the improvements of current and future products.- Improved system diagnostics (POST) through debug and code analysis.- Worked with the Solaris Engineering Group to enhance the OS for better CPU RAS.- Drove down system kDPM yields below the targeted limits.- Drove down customer FIT rates and improved component reliability.- Provided input on critical customer escalations (Executive Alerts).- Product Lifecycle Management (PLM), especially using Agile.

Newark, California

- Supplier Engineer for SPARC (UltraSPARC I, II, and III).- Responsible for sustaining activities, including debug and supplier RCA.- Reduced no-defect-founds, and other cost drivers.- Internal Auditor for ISO-9001. Also familiar with Six Sigma.- Computer skills include MS Word, Excel, Powerpoint, Visual Basic, Unix and C programming.

Redwood City, California

Process and Quality Engineer (October 1993 - August 1997) - Developed quality control program to lead improvements in yields and throughput.- Interfaced with customers to ensure all of their specifications and requirements were met.- Managed weekend shift: - Managed all employees’ performance and schedules. - Started up entire facility each morning, and shut down in evening. - Problem solve all issues (facility or process) that arose during shift.