Edward Finn Email & Phone Number

I have an LLC and will consider small Hardware / Firmware projects part time.

Feasterville-Trevose, Pa, Us

Hardware and firmware design of Inverters for emergency lighting equipment

Self Employed Contract Engineering - Hardware and Embedded Firmware for proof of concept engineering prototypes. Fast high voltage slew rate fiber switch and embedded medium power laser driver and TEC temperature controller.

Analog and digital design support on low power embedded product line.

Analog Circuit and Embedded Hardware and Software Design.Supporting Variable Area flow meters and Capacitive Manometer absolute pressure monitoring device product lines.

Berwyn, Pa, Us

Hardware product design including spice modelling and lab evaluation of analog signal processing blocks for RF admittance measurement instruments. Board and product testing and validation. - Embedded H/W design for extreme low power designs for Industrial Instrumentation in hazardous environments. - Supported updates to product designs for agency approvals and component obsolescence issues.

-product development of a wireless communication system for control of High Intensity Lighting networks.-hardware and software integration of a Zigbee radio device and embedded ARM microcontroller to control a lighting mesh and collect status and execute power saving algorithms.-used Keil development tools and C language to implement a command protocol to send and recieve data and commands to mesh clients.

Palo Alto, California, Us

member of small physical design group which performs SOC PD function and develops custom timing closure tcl and perl and cshell procedures to overcome shortcomings of the physical design CAD tools at 40nm, including fixes for SI effects such as upsizing, repeating, cloning of targeted instances/nets. Custom scripts (csh, tcl, perl) for auto repairing drv violations (FO, Cap, trans).

Santa Clara, California, Us

Physical Design solutions for timing closure of 65nm SOC designs.

Santa Clara, California, Us

physical design and timing closure solutions for 110nm and 80nm SOC designs.RC extraction correlation of place and route tools to sign off extractor.

Hillsboro, Oregon, Us

complete setup (from scratch) of Cadence First Encounter tech files and place and route flow for in-house developed library for a 90nm process. library abstraction and assistance to setup of hercules extraction process.using FEtcl scripts and cadence db access commands.

Eindhoven, Noord-Brabant, Nl

return to a technical role during this time. performing physical design using Synopsys Apollo and Astro tools.

started as a design engineer doing many aspects of asic design, and was promoted to design center manager doing many customer proposals and leading a group of local and remote design engineers.

Architectural design and front end implementation of a communication protocol IC for the company's terminal and printer emulation product line. Proof of concept prototyping partitioned into 4 xilinx fpga's, and design entry and simulation in Valid logic CAD system. I was coordinator with contract house to implement into an IC using VLSI Technology as foundry.

Charlotte, North Carolina, Us

design of micro-power analog instrumentation front end using discrete, hybrid, and custom analog IC methods for their industrial pressure transmitter devices. Developed a gate array A/D interface to connect the analog channels to the low power cpu.