Eric Crabill Email & Phone Number

Responsibilities in the Adaptive and Embedded Computing Group include:• Technical, Product, and IP Marketing for Radiation Effects and Solutions• Technical, Product, and IP Marketing for PCIe Subsystems and Solutions• Technology Liaison for Field Training

Responsibilities included the following:• Technical Marketing for Configuration - the Essence of Xilinx• Technical, Product, and IP Marketing for Radiation Effects and Solutions• Technical, Product, and IP Marketing for PCIe Subsystems and Solutions• Technology Liaison for Field Training, Virtual Roadshows, and Demos

Architected, implemented, verified, validated, and documented the Xilinx Soft Error Mitigation LogiCORE for Virtex-6. Conducted radiation experiments at UC Davis cyclotron to evaluate SEU mitigation performance. Mentored team members to derive the Xilinx Soft Error Mitigation LogiCORE for Spartan-6.Upgraded the Xilinx Soft Error Mitigation LogiCORE for 7-Series. Researched, developed, and implemented an algorithmic multi-bit repair method. Architected and prototyped the Xilinx Soft Error Mitigation LogiCORE for UltraScale architecture.

Managed IP development and design services. Coordinated international teams to satisfy aggressive schedules of customers, completing more than 30 projects. Provided field support for Western Hemisphere and Europe, including training collateral for iCE65 FPGAs.

Evaluated future Xilinx architectures for PCI, PCI-X, and PCIe readiness and provided feedback to planning and design teams.Collaborated with contract board manufacturing service to yield solutions for three starter kits. Specified, designed, and implemented board test designs, out-of-box demos, and reference designs.Authored application notes covering a variety of topics: XAPP456 (Custom PCI Timing Budgets), XAPP457 (Power and Configuration for PCI Applications), XAPP458 (Implementing DDR2-400 Memory Interfaces), and XAPP459 (Eliminating I/O Coupling Effects). Contributed to XAPP460 (Video Connectivity using TMDS).

Managed a small team working on physical layer implementations for the first generation Xilinx PCIe LogiCOREs; designed and implemented up to the data link layer boundary with a variety of internal and external gigabit serial transceivers across Virtex-II Pro, Spartan-3, and Virtex-4.Managed a small team to develop a verification environment for the Xilinx PCI-X LogiCOREs. Designed, implemented, and documented these, including PCI-X 64/133 and customized cores for transparent bridging applications. Designed, implemented, and documented the Xilinx PCI LogiCOREs including PCI 64/66. Maintained these products for nine years across more than a dozen Xilinx architectures.Designed compliance test cards and applications to validate Xilinx LogiCORE solutions at PCI-SIG compliance workshops.

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