Pdk Engineering Intern
- Designed and adjusted layouts for various experimental superconducting chips using Cadence Virtuoso.- Debugged and developed to existing DRC and LVS rulesets to ensure for multiple microprocessor technologies.- Migrated and converted DRC and LVS rulesets from the Cadence-Assura run language to the Mentor-Calibre language.- Created multiple QA test cases in Cadence Virtuoso to certify the proper functionality of the written DRC ruleset files.