- Led a team of four researchers and engineers developing a PoC cryptographic hardware accelerator.- Defined the instruction set, micro-architecture, submodule blocks, and their interfaces.- Performed code reviews, and oversaw the development of RTL modules, integration, and ASIC synthesis.- Held daily stand-up, sprint planning, retrospective meetings, and backlog grooming in a Scrum Agile framework.- Delivered project documentation, results reporting, and quarterly… Show more - Led a team of four researchers and engineers developing a PoC cryptographic hardware accelerator.- Defined the instruction set, micro-architecture, submodule blocks, and their interfaces.- Performed code reviews, and oversaw the development of RTL modules, integration, and ASIC synthesis.- Held daily stand-up, sprint planning, retrospective meetings, and backlog grooming in a Scrum Agile framework.- Delivered project documentation, results reporting, and quarterly presentations. - Received the Outstanding Team award from Huawei's Canadian Research Institute. Show less

- Worked on hardware acceleration research for Fully Homomorphic Encryption (FHE) using FPGA clusters.- Developed and tested RTL modules with AXI stream interfaces in Verilog. - Worked with Number Theoretic Transform (NTT) hardware module with high polynomial degrees.- Performed synthesis, implementation, and timing closure using Vivado. - The research work was published in a conference paper in IPDPS 2023.

- Worked on securing the GO device and mitigating security threats.- Performed On The Air (OTA) firmware updates that run on over 1 million deployed devices.- Implemented internal flash HAL for ARM MCU.- Ported bootloader, start-up code, and linker files for ARM processor.

- Contributed to different research areas in the hardware security lab including Physical unclonable functions (PUFs), Electromagnetic fault injection (EMFI), chip decapsulation and preparation for photon emission microscopy and laser fault injection. - Implemented a Bistable Ring Physical Unclonable Function (BR-PUF) and its variant TBR-PUF on a Spartan-6 FPGA with a UART interface to receive and send challenge-response pairs.- Wrote Python scripts to automatically deliver and receive… Show more - Contributed to different research areas in the hardware security lab including Physical unclonable functions (PUFs), Electromagnetic fault injection (EMFI), chip decapsulation and preparation for photon emission microscopy and laser fault injection. - Implemented a Bistable Ring Physical Unclonable Function (BR-PUF) and its variant TBR-PUF on a Spartan-6 FPGA with a UART interface to receive and send challenge-response pairs.- Wrote Python scripts to automatically deliver and receive thousands of challenge-response pairs and evaluate PUF properties such as noise, bias, and challenge-response hamming distances.- Performed manual placement and routing using ISE PlanAhead tool to ensure PUF properties.- Improved the PUFs properties using XOR techniques reaching near-ideal properties, making the PUFs more resistant to modeling attacks.- Worked on electromagnetic fault injection on RISC-V processor and reported skipping multiple instructions. - Managed to breach a secure boot using EMFI by skipping branch instructions.- Decapsulated SiFive RISC-V chips for photon emission microscopy and laser fault injection research and prepared custom developement boards soldering QFN chips. - The PUF and EMFI work were published in two conference papers in HOST 2020 and ISQED 2020. Show less

- Delivered tutorials and ran lab sessions for for ECE-124 (Digital Logic Design), ECE-222 (Digital Computers), ECE-224 (Embedded Systems).- Ported RISC-V softcore to university FPGAs building an SoC with the needed peripherals using Altera QSYS.- Prepared startup codes and compiling scripts for students' use.- Redesigned lab manuals and lab example codes to accommodate RISC-V instead of existing ARM labs.- Received the TA Distinction award from the ECE department for Fall 2018.

- Performed hardware-in-the-loop (HIL) testing for vehicle active safety systems.- Designed and implemented test cases using Java and CAPL.- Worked with CAN, Ethernet and FlexRay protocols using CANoe tool.

Supervisor: Prof. Anupam Chattopadhyay- Collaborated in ASIC benchmarking of CAESAR Authenticated Encryption competition candidate algorithms.- Implemented an area-efficient CLOC cipher using Verilog and used Synopsys Design Compiler tool for Synthesis.- Improved area by 29.29% and throughput per area by 20.6%.- Work was published in a conference paper in ISVLSI 2018 and an IACR ePrint Archive.

Supervisor: Prof. Mohammed Morsy Farag- Implemented an instruction set extension to MIPS ISA using Codasip Studio tool to accelerate Secure Hash Algorithm SHA-3.- Improved the speed by 25% by implementing an instruction set extension and 61.4% by building a specialized co-processor.- Implemented SHA-3 algorithm using MIPS assembly before and after the extension.- Work was published in two conference papers in ICM 2016 and ASAP 2016.

- Worked on Questasim tool coverage quality assurance.- Used shell and TCL scripting for internal QA automation purposes.

- Under the umbrella of the LowRISC open-source community I ported Arduino libraries and drivers to PULPino open-source microcontroller based on RISC-V processor.- Ported GPIO, interrupts, timers, UART, SPI and I2C interfaces.- Used C/C++ for main development and assembly for C runtime startup code.- Work was merged to Pulpino's project Git repository.