An Electronics and Communications Engineer and holds a role as an Executive Staff Member/Design Department Manager with over 19+ solid years of hands-on experience in semiconductor companies as IC layout engineer. Currently leading a team in the Design Department at SilVer as Department Manager. Known as an expert in physical design skills in IC layout ranging from non-volatile Flash Memory (NOR), chipset, standard cell, and FPGA.

• Owned custom digital PLC and CIB layout in 40nm technology with modular design and small footprint of 44um by 48um.• Instrumental in delivering custom digital PLC and CIB layout in 28nmFDSOI technology with modular design and small footprint of 36um by 38um.• Experienced in independently learning from design rule manual for 40nm and 28nmFDSOI technologies that enabled a team of 5 to start custom PLC layout implementation.• Provided layout support and owned simple to complex blocks… Show more • Owned custom digital PLC and CIB layout in 40nm technology with modular design and small footprint of 44um by 48um.• Instrumental in delivering custom digital PLC and CIB layout in 28nmFDSOI technology with modular design and small footprint of 36um by 38um.• Experienced in independently learning from design rule manual for 40nm and 28nmFDSOI technologies that enabled a team of 5 to start custom PLC layout implementation.• Provided layout support and owned simple to complex blocks for different Lattice products in 65nm, 40nm and 28nmFDSOI technologies.• Worked in different parts of FPGA chip like owning/supporting PLC, CIB, flash memory and analog mixed signal circuits and chip integration.• Significant experience in handling large complex critical blocks, floorplan creation and signal integration, Engineering Change Order implementation, physical verification analysis and debug, violation waiver approval and documentation, and chip GDS tapeouts.• Proficient in physical verification flows and tools: DRC, LVS, Antenna, Density, EMIR, ESD, Latchup, DFM, Hercules, Calibre, PVS.• Knowledgeable in basic Unix commands.• Experienced in tapeout process working with foundry and IP sign-off with 3rd party vendor.• Layout technical project lead for Lattice’ first 40nm FPGA project with a team of 52 engineers from 3 different Lattice sites while stationed in the US for 9months.• Traveled to US 5 times for early project engagement.• Senior layout staff managing seven direct reports. Identified and worked on career development, provided constructive feedback, guidance and mentorship, and created/delivered performance annual reviews.• Led a team of 40 from 3 different Lattice sites (US, Philippines, and China) to deliver all custom Lattice IPs required for Lattice’ first 28nmFDSOI FPGA project. Show less

• Delivered standard logic cells layout using a 28nm technology to be used in building logic circuits. • Worked on compiler blocks such as sense amps, mux and IO circuits layout from implementation to verification using a 28 nm technology.• Fast learning capability of the new tool needed for layout implementation which includes floor plan, routing and verification, and implementation of Engineering Change Order on a tight schedule.• Adjusted and communicated well in the client’s… Show more • Delivered standard logic cells layout using a 28nm technology to be used in building logic circuits. • Worked on compiler blocks such as sense amps, mux and IO circuits layout from implementation to verification using a 28 nm technology.• Fast learning capability of the new tool needed for layout implementation which includes floor plan, routing and verification, and implementation of Engineering Change Order on a tight schedule.• Adjusted and communicated well in the client’s working environment in the US for a 5-month duration assignment. Show less

• Worked in all sections of NOR flash memory on various Intel process technology.• Experienced in systematic planning and execution of CMOS layout designs from device placements, floor plan, routing, physical verification (DRC, LVS, ANT, DFM, DENSITY), and implementation of ECO.• Rendered off-shift hours and 24/7 supports to eliminate the risk of schedule impact.• Efficiently managed up to 10 resources as section lead by providing clear directions on job scope, plans and schedules… Show more • Worked in all sections of NOR flash memory on various Intel process technology.• Experienced in systematic planning and execution of CMOS layout designs from device placements, floor plan, routing, physical verification (DRC, LVS, ANT, DFM, DENSITY), and implementation of ECO.• Rendered off-shift hours and 24/7 supports to eliminate the risk of schedule impact.• Efficiently managed up to 10 resources as section lead by providing clear directions on job scope, plans and schedules within a given date of completion.• Worked closely with cross-functional teams like design engineering, design automation, integration and tape-out group both local and international (US, Malaysia and China) for design-related changes and significant need-to-know. Show less

• Worked in all sections of NOR flash memory on various Intel process technology.• Experienced in systematic planning and execution of CMOS layout designs from device placements, floor plan, routing, physical verification (DRC, LVS, ANT, DFM, DENSITY), and implementation of ECO.• Rendered off-shift hours and 24/7 supports to eliminate the risk of schedule impact.• Efficiently managed up to 10 resources as section lead by providing clear directions on job scope, plans and schedules… Show more • Worked in all sections of NOR flash memory on various Intel process technology.• Experienced in systematic planning and execution of CMOS layout designs from device placements, floor plan, routing, physical verification (DRC, LVS, ANT, DFM, DENSITY), and implementation of ECO.• Rendered off-shift hours and 24/7 supports to eliminate the risk of schedule impact.• Efficiently managed up to 10 resources as section lead by providing clear directions on job scope, plans and schedules within a given date of completion.• Worked closely with cross-functional teams like design engineering, design automation, integration and tape-out group both local and international (US, Malaysia and China) for design-related changes and significant need-to-know. Show less