Tunc Eroglu Email & Phone Number

Chandler, Az, Us

San Jose, Ca, Us

San Jose, Ca, Us

Working on SystemC TLM modeling of major blocks, behavioral simulation modeling of device primitives, power estimation and reporting of all FPGA and ACAP devices. Supervising development of new tools built around SystemC modeling and power estimation capabilities of the team.

San Jose, Ca, Us

Working on the development and optimization of Unisim libraries for current and future products.

San Jose, Ca, Us

Member of Vivado Device Simulation group. Working on the development and optimization of Unisim libraries for current and future products.

Santa Clara, Ca, Us

Responsibilities cover all aspects of Tabula IP and Reference Designs from concept to implementation, release, QA and customer delivery. As part of the Tabula Systems Group, trained and managed a dynamically re-sized group of 5-10 engineers located in India with nearly 24/7 supervision and support. Worked with partners to port their IP to Tabula's ABAX2 fabric. Drove Software Quality of Results by working with all SW groups, created regression and release infrastructure for IP designs allowing regressions to exercise arbitrary subset of available parameterization and releasing the same. Worked closely with SW architecture team to identify issues, find solutions and prioritize SW development tasks based on IP and customer needs. Investigated the market, evaluated products, contracted the job, specified Tabula's requirements and managed implementation of a web-based IP Management System (IPMS). Worked with other stakeholders to integrate the IPMS to Tabula customer portal.Managed customer documentation of Tabula and partner IP and Reference Designs. In addition to IP documentation, shared the Content Editor responsibility for the entire Tabula customer documentation site running on Confluence starting from evaluation of the available platforms, then setting up the documentation flow and finally implementing the flow to release 200+ documents over 15+ release cycles.Worked closely with Application Engineering team to prioritize IP needs, provide technical support with Tabula IP and answer customer questions, meeting with customers when necessary.Worked closely with Manufacturing team to provide test designs to qualify parts and to understand silicon issues that need to be worked around.Worked with other members of the systems group in planning and implementing system level designs, designing development boards, bringing up boards, designs and systems.

Santa Clara, Ca, Us

Drove synthesis, place and route tool suite development by creating sample designs, simulation test benches, regression test suites, filing bugs, tracking progress against goals and presenting issues and solutions in daily meetings to the organization and regular meetings with customers. Supported chip bring up power and timing characterization by designing parameterized, targeted test circuits and regression suites. Ported customer designs and third party IP to Tabula ABAX architecture. Helped develop IO logic primitive library supporting DDR3 and similar high data rate complex IO interfaces. Supported customers through RTL port, PCB design, board bring up, regression test stages. Interfaced customers, marketing, architecture, SW and HW teams as well as contractors and representatives.

Milpitas, Ca, Us

Sr. Staff Systems Engineer in Audio Video Business Unit responsible for media player controller SOC design. multi-chip module design, project management and hardware support though all the phases of a MP3 player product's life cycle. Have been involved with the system design of most of the Sansa line of MP3 players of SanDisk for the last two years.

Staff Engineer II in Data Storage Business Unit Application Team. Designed prototype systems for the evaluation, characterization and debugging of the Power Combo line of mixed signal ICs for disk drives.Designed PCB, FPGA logic, MCU firmware and PC GUI for every new IC.Supported customers and field application engineers in the bring up of the chips in customers' systems and debugging elusive bugs.

Sunnyvale, Ca, Us

Designed the digital control logic of a CMOS, 3D time-of-flight camera chip. Fully responsible for the design, documentation, procurement and manufacturing of FPGA based development systems.Supported IC design team in verification of digital IC and camera sensor arrays.

Ankara, Tr

Ms Ee, Microelectronics

Bs Ee, Microelectronics, Circuits And Systems