Eric Christie Email & Phone Number

Provo, Ut, Us

Boise, Idaho, United States

Embedded with the DRAM Node Development Design team, focused on proving leading-edge process and design techniques. - Developed 3D models of test chip layout for communicating advanced structures and identifying areas of innovation. Fully documented a tutorial allowing any engineer to model their own layout. - Evaluated emerging simulators for replacing current Sense Margin simulation processes, potentially reducing verification timeline from weeks to days while preserving necessary functionality

Provo, Utah, United States

Researching Ultra-Low Voltage ADC implementations in the Micropower Circuits Laboratory. Involved in multi-disciplinary teams to further research related to Quantum X-rays, Martian particle CDMS, and novel carbon fuse P-ROM fabrication.- Published 5 times, twice as first author- Presented research results in formal and team settings- Actively coordinated with multi-disciplinary teams to accomplished shared tasks- Mentored new undergraduate researchers and provided technical training relevant to their projects

Assist in design and testbench generation for IO’s using Cadence Virtuoso Schematic Capture and ADE Assembler. Exposure to multiple processes including planar and FinFET. - Designed an I2C/I3C compliant GPIO/ODIO hybrid IO driver in TSMC 65nm using Cadence Virtuoso Schematic Capture- Created testbenches to verify IO functionality and spec compliance using Cadence ADE Assembler, including testing over 2^6+ corners- Modeled IO libraries in Verilog for initial customer delivery

Provo, Utah, United States