Eric Dormer Email & Phone Number

I am based in Ottawa Canada currently but happy to work on-site or hybrid or remote anywhere in the world for a permanent or contract position. I can relocate if needed, I am highly mobile.I am a Canadian citizen, but I can also work in the USA using a simple TN1 visa. It is simple, all I need is a job offer or contract offer letter, and I do the rest. I renew it at the Canada/US border every year, it is no burden for the client or employer. I can also do work for clients in other countries on a corporation to corporation basis. Note I cannot work for clients in countries that are under sanctions by the USA or Canada (Russia, North Korea, Iran, etc.)I am happy to do remote work for US or International clients. I frequently travel to the USA, Europe, and the Far East. I am happy to visit my client during project kickoff, key milestone reviews, and lab integration and testing. Or when necessary, I can relocate to my client's location for the duration of the project.I am eligible for ITAR clearance. I am not a US citizen thus I am not eligible for some U.S. based jobs (typically Defense related) that demand US security clearance.

International Travel and summers at my Cottage No Client, just some time to relax and enjoy life after Covid-19 was finally over. Several cruises to Caribbean, Hawaii, San Diego, British Columbia, and extensive adventure travel with a backpack to Thailand, Vietnam, India, Dubai, Mexico. And summers at my waterfront cottage in Quebec 1.5 hours north west of Ottawa.

Debug system firmware on a portable battery powered bedside blood analysis device. Define bandwidth efficient protocol to send command and response messages to and from device and nearby Android or PC based controlling computer. Implement bluetooth low energy (BLE) interface to Android portable computer to manage device and upload test results. Implement a regressionable firmware test environment running on either a STM32 and windows platform (with different levels of hardware system abstraction), connected to git library and devops flow to ensure git pull_requests can be tested fully automatically prior to approval. This allowed safe ongoing development of firmware without introducing bugs to previously functional code.

Debug system verification testcases on very large math processor ASIC. Methodology was built around C++ programs running on multiple on-chip processors. Debug by reviewing log files, collecting and inspecting waveforms, code inspection of testcase code, test infrastructure code, and SystemVerilog RTL. Utilized Palladium and Zebu verilog emulators.

London, United Kingdom , Gb

Convert C++ implementation of Combinatorial Optimization algorithm to run on FPGA. Target is Ultrascale Xilinx. Algorithm implements heuristic solution to find S vector to minimize Ising Energy given a particular J matrix. Uses C++, Python, Bash, Vivado, SystemVerilog, Icarus Verilog simulator, GTKWAVE viewer. Extensive matrix operations in FPGA using floating point numbers with variable exponent and mantissa bits.

Middleton, Wisconsin, Us

Evolve existing C firmware on a battery powered portable data collection device. Transfer data to host Windows 10 Surface Pro tablet using both USB and Bluetooth BT121 Module. Use TI Code Composer IDE (Eclipse) and target C code to TI MSP430 processor. Use Silae logic analyzer. Use Git. Use Perforce.

Low Power FPGA Design in Verilog, API Interface to FPGA in C. Developed a Lattice Ice40 Micro Power FPGA (ICE40UP5K specifically) to collect data periodically from 2 MEMS devices using slow SPI busses, and then raise interrupt, and deliver combined data rapidly over a fast SPI bus. Produced verification plan, and testbench and a dozen testcases to verify design using Verilog. Designed test card to confirm correct interaction with host STM32 CPU including download of bitfile, and subsequent interrupt handling. Created C API for operation of FPGA and its subtending MEMS devices, to operate under FreeRTOS. Confirmed correct operation on actual production circuit card.

Charlotte, North Carolina, Us

Short Contract to debug two Dozen Circuit Boards and do Failure AnalysisAs part of a quality assurance process, debug two dozen circuit boards and determine the root cause of failures, and recommend solutions to avoid future problems. The board contained several stepper motor control circuits containing a mix of digital and analog hardware. This involved collaborating with production line staff, QA staff, detailed testing using an automated Engineering Probe and Test workstation, Oscilloscope, Multimeter, and then recording and analyzing data using spreadsheets, communicating findings to team members in daily brief status meetings, and writing a more detailed report with full findings and recommendations.

Toronto, Ontario, Ca

Cypress FX3 Code, Windows Driver Debug, USB3 interfaceDebug P-port state machines in Cypress FX3 chip to transport USB3 data at high speeds between two Windows 10 host systems. Review and measure performance of Windows USB3 Drivers, and LIBUSB drivers to examine throughput and maximum bandwidth limitations on Windows 10 systems. Used lots of C and C#. Used libusbdotnet C# library. Used P-Port Designer from Cypress. Used EasyUSB Suite (Eclipse) from Cypress. Used Microsoft Visual Studio with C#.

Arlington, Va, Us

Digital Flight Data Recorder for Civilian and Military AircraftDefined chip architecture, VHDL coding, documentation, and testing of Altera Cyclone V FPGA implementing NIOS2 processor, Ethernet Interface, several DMA engines, several SATA interfaces, and other miscellaneous SOC blocks (on chip RAM, I2C, UARTs, timers, DDR3 interface, etc). Created self-checking VHDL test harnesses with half a dozen functional testcases. Created firmware code to run on this FPGA bare-metal (ie- with no operating system) to do command parsing of received Jumbo Ethernet packets, perform operation, and then create and emit a response packet. Created self-checking software test environment using C to test the firmware on different abstraction-level models of the chip, and on the real hardware. Product is for military-aerospace application.

Firmware Enhancement and RF Testing of Powerline Monitor for Electrical Distribution SystemsUpdated C firmware for a 2.4 GHz Zigbee network device based on NXP Semiconductor MKW24D512 chip. Made changes to support an additional I2C slave device, to enable various RF relays, to enable RF beam forming intended to increase the range. Participated in RF testing of enhanced circuit.

Us

16 x CSI-2 Camera Multiplexer FPGAUsing MicroSemi SmartFusion2 FPGA, designed and implemented system to multiplex together pixel streams from 16 cameras composing data into UDP packets to be emitted over Gigabit Ethernet. Used ARM processor, with full set of SOC standard reusable components including UART, I2C Master and Slave, SPI Master and Slave, Timer, DDR3 External Memory Interface, Quad SPI Flash External Memory Interface, on-chip SRAM bulk memory, on chip FLASH memory, on-chip SRAM Mailbox Memories, Gigabit Ethernet MAC block. Other custom datapath blocks included pattern generators, CSI-2 interface blocks, line buffers, multiplexing logic, logic to extract and insert packets from datapath and route to control block, and packet queuing logic.

Software Testing of VxWorks Real Time Operating System (RTOS)Done to achieve Avionics DO-178B Compliance Certification. Unit tests, Linkage and Binding tests. Used coverage tools to ensure code coverage and branch coverage. Used stubs for lower level functions. Created extensive C test harnesses. Worked with software tool infrastructure that documented all requirements, all features, all test artefacts, and captured all test results. All tests were self checking. All test programs were reviewed and signed off by detailed code review with team.

Verilog Coding, TCL Script Creation and Lab Debug of Board containing Altera MAX10 FPGA Created Verilog FPGA Code and testbenches, and board test environment for Altera FPGA dealing with stereoscopic image data compression system. The board was provided by the client. The test suite included extensive TCL scripts. Did board level testing of a variety of peripherals including DDR3 memory, SPI FLASH memory, UARTs, I2C master and slave interfaces. Board contained image sensors, and FX3 chip from Cypress (to interface to USB2) which connected to an Android Tablet. Tablet displayed compressed and uncompressed images. Repeated Synthesis, Place and Route, and Static Timing via Quartus. Used SignalTAP and TCL scripting from Altera Quartus Console extensively. Used Quartus Prime PRO 16.1 and QSYS.

Software Design for Text Parsing PINPAD Messages using C/C++Designed and implemented module providing interface to handheld PINPAD for debit card and credit card transactions, running on in-car LINUX based TaxiCab system. This involved parsing messages emitted from PINPAD, and composing messages to send to it. Used TCP/IP Sockets. Had to support a new PINPAD brand, and make it behave same as 2 legacy brands in terms of operation of the rest of the legacy system. Code development using Eclipse with a GNU Toolchain targeting Linux running on Windows. GIT library management system. Issue tracking and closure using JIRA.

Mobile Terminal GUI Design on Linux System using Qt 4.8 and C/C++Designed and implemented graphics user interface (GUI) module for an in-car TaxiCab system to drive an LCD screen connected by USB2 to an existing modestly powered embedded system running Linux. This involved C and C++ real time software development of two major modules for Embedded Processor in an existing legacy TaxiCab application consisting of a few dozen legacy modules. GUI Development using Qt 4.8. Code development using Eclipse with a GNU Toolchain targeting Linux, running on both on Linux (Ubuntu) and Windows. GIT library management system. Issue tracking and closure using JIRA.

Kanata, On, Ca

4K UHD Video Reusable Block Design, on Altera Arria FPGA Developed reusable IP to implement 12G video solutions, including a SQD and DEMUX_2SI solution to combine 4 3G links into a 12G link. (ie- 12 Gigabit/second.) which supports UHD TV standards, also known as 4K TV. Completed designer verification to pass UVM testcases provided by another team member. Evolved and implemented UVM testbench and ran testcases to achieve high coverage. Agile Development methodology followed, with rapid iterative design process, and frequent “stand-up” meetings to ensure design team overcame mixups rapidly and stayed focused on sprint goals.Multi-person development teams all used GIT as we did feature development, and ultimately passed it through a web-based regression control environment (JENKINS) before our feature was accepted into the main development branch. Used REDMINE for issue tracking and closure.

Kanata, On, Ca

Designed HiSPi Stereoscopic Image Data Compression Chip using Altera MAX10 FPGACreated specification for FPGA dealing with stereoscopic image sensor and delivering a lower bandwidth, frame aligned version over USB2. Implemented using Altera Video IP suite components, including CVI, CVO, and Video Framebuffer2 and Video Scaler blocks. Implementation in Altera MAX1050 technology. Included NIOS2 processor, I2C master and slave, SPI, UART, DDR3 Memory interface, FLASH Memory Interface, and HiSPi Image Sensor Interface, and multiple PLLs. Extensive coding in Verilog.

Ottawa, Ontario, Ca

Created a Board Support Package (BSP) coded in C language for evaluation board. This provided a command line interface allowing writing and reading memory locations, script management, command history, local variables, and so on. Created drivers for several hardware components on the evaluation board and evolved other existing drivers to simplify what was there (for example the I2C interface to ID PROM, and the SPI interface to off-chip devices). Automated compilation/linking scripts. Used Makefiles, BASH and TCL to automate tasks using scripting. Used the GNU tool chain for compiling, linking, and to do automated testing, and in-circuit debugging. Used Eclipse for development and debugging (GDB) of C code. Library management using Subversion (SVN).

Ottawa, Ontario, Ca

High speed A-to-D interface design with 8 lanes each 6.25 gigabits per second into Xilinx JESD402B decoder IP block. Creation of alternate JESD204B encoder and decoder blocks in clear text Verilog. Extensive use of ChipScope (Logic Analyzer function inside FPGA) for lab debugging. FPGA RTL design and verification, synthesis, place and route, static timing analysis using Xilinx Vivado toolset (13.4, 14.1) .

Ottawa, Ontario, Ca

C-to-gates conversion tool evaluation (HLS). Matrix hardware acceleration for Nearest Neighbour Algorithm of high speed real time image processing.

Charlotte, North Carolina, Us

Nuclear Reactor Simulation using PERL and Blender3DWorking under direction of Physics PhD, evaluated performance of advanced Fission Reactor Designs by varying isotope mixes and concentrations, and mechanical parameters. Wrote PERL scripts to convert high level parameters into extensive "Fortran-like" programs to drive a numerically intensive nuclear simulation program. Obtained results for fission rates, power production densities, neutron efficiency, etc. Wrote PERL scripts to extract key results and present them in easy to understand tables. Created PERL scripts to parse geometric information for reactor cores and emitted it in triangle format which was then viewed in BLENDER 3D rendering program.

High Speed Eye Sampling using Altera FPGAImplemented Altera FPGA to interface with several very hi-speed Analog to Digital Converter chips that do sampling of a repeating PRBS code at very precise intervals relative to the bit period of the code sequence. In this way the eye diagram is built up. The FPGA moved the sample data from the various sampling domains, into a core domain, and ultimately delivered it to a host system. However, the main the challenge of the system was to implement a unique and novel delay locked loop algorithm controlling the sampling clock to allow very precise sub-nanosecond time resolution between samples on multiple channels, giving inexpensive and unparalleled precision to eye diagram capture for the Automated Test Equipment marketplace.

FPGA Design Tool Creation using PERLExtensive Perl and Python Script development. Created complete set of FPGA productivity tools including language pre-processors, software register interface builder, and a Verilog language extension. Tool automatically generates power-on self-test C language firmware routines exercising low level hardware, plus creation of C language code stubs in include file to provide symbolic names for fields in registers to support firmware drivers. Also evaluated Mercurial code revision management system.

Corporate Website Development using HTML, JavaScript, CSS, PHP, mySQL.

Involved in several start-ups, sometimes as a founder where I provided financing

Altera Ottawa Technology Center, Ottawa (Altera Inc. is a technology firm with international operations) Responsible for:• negotiating international technology development agreements with foreign clients• project management of multi-site technology development• intellectual property licensing and patenting

Founded and built this 25-person telecommunication chip design service company, serving clients in North America, Asia, and the Orient.• Designed silicon chips, FPGAs, firmware, software. Contract negotiation, administration.• SONET and ATM solutions. T1 to T3 Solutions. Custom Glue Logic chips.• Sold it to Altera Corporation and became their local DirectorCreated tools and a build/regression environment to allow FPGA development and verification. Used a combination of C-language text transformation programs, and AWK. Created a GPS receiver chip, and a C-language simulation environment to ensure coarse and fine signal acquisition worked.

Ca

Board designer, chip designer, system architect, and ultimately Design Team Manager of 8-person chip design team, working on telecommunication products. High Speed SONET/ATM switches.Using the C language I created a simulation management environment, including a dynamic load sharing program to dispatch simulation programs on available workstations based on their hardware capacities and current load levels, then collected the results and relaunched any jobs that failed to complete.

Dorchester, Ontario, Ca

Chip design of programmable attenuator. Programmable hearing aid design. Software development for in-the-ear audiometer. Board layout for agricultural digital weigh scale. C software coding for embedded system for weigh scale.

B.A.Sc., Electrical Engineering, With Computers

Paralegal Diploma

M.B.A., Finance, Public Policy