Eric Herrmann Email & Phone Number

Mountain View, California

United States

Focus: completing the design, fabrication, testing, and simulation of \(1\mu m\) critical dimension novel gate-controlled resistive memory devices using transition metal oxides. Accomplishments: Designed, fabricated, tested, and modeled a new gated memristor device, filed a provisional patent for it through the University of Cincinnati, demonstrated its.

Sunnyvale, CA

- Used Cadence Design Entry to create the schematics for a test board for the next generation line module, which was used for high speed electrical interface testing, generating control signals, and eventually automated testing of all backplane signals- Personally completed requirements evaluation, PCB layer specification, schematic creation, layout.

Sunnyvale, CA

- Worked on validation, integration, and debugging of high speed SerDes (serializer/deserializer, 28 Gbps) for the next generation on-board electrical interfaces for optical communication servers- Worked from the first test chip through production of ASICs on board- Worked closely with the IP designers to find silicon bugs and room for improvements.

Dayton, Ohio Area

High school summer internship writing applications for processing drone imagery in C++ using video and image processing libraries. Also worked on SLAM(Simultaneous location and mapping) algorithm testing.

Master’S Degree, Electrical And Electronics Engineering, 3.97

Focus: VLSI Thesis: A Novel Gate Controlled Metal Oxide Resistive Memory Cell and its Applications

Bachelor'S Degree, Electrical Engineering, 3.97

Activities and Societies: IEEE Engineering Tribunal Intramurals Theta Tau Professional Engineering Fraternity Tau Beta Pi Honors.