Eric Howard Email and Phone Number
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Eric Howard personal email
Innovative professional software engineer with over 26 years of experience with complex algorithms, with particular focus on integrated circuits and computer aided design. Has particular expertise with timing analysis, synthesis and floor-planning. Highly intuitive, with an ability to understand complex situations and find robust solutions. A dedicated team player, with a deep understanding of high quality, well-tested, and on-time software. Comfortable leading development teams when necessary.SKILLS & TECHNOLOGIES• Expert software developer and architect.• Expert knowledge of IC CAD algorithms: timing analysis, synthesis, & floor-planning.• Have direct, hands-on experience with o C, C++, Python, JavaScript, Skill, Tcl, JSON, SQL, Django. o IC Compiler, Design Compiler, Genus, PrimeTime o Floorplanning & timing analysis data formats: Liberty files, LEF & DEF files, SDC. o Cache coherency, Network-on-chip, and Clock & Reset hardware modeling. o Multi-threaded software development, Inter-process communications, SunGrid, and RPC. o Agile development, unit-level testing, regression testing, and continuous integration. o Software team management, including project planning and scheduling.
Arteris
View- Website:
- arteris.com
- Employees:
- 356
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Principle Product Architect And Senior Director EngineeringArterisSanta Clara, Ca, Us
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Principle Product Architect / Senior Director EngineeringArteris May 2023 - PresentCampbell, Ca, Us
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Senior Product Architect / Senior Engineering ManagerArteris Jun 2020 - May 2023Campbell, Ca, Us
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Senior Corporate Application ArchitectArteris Jun 2018 - Jun 2020Campbell, Ca, Us
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Senior Software EngineerArteris Sep 2014 - Jun 2018Campbell, Ca, UsImplemented a streamlined SDC constraint generator for a cache coherent network on chip design tool. Created a regression environment to automatically do code coverage and launch regression tests on a compute grid.Implemented physical synthesis support for Network-on-Chip topology synthesis. Enhanced linear solver implementation to determine SOC interconnect pipeline stage insertion points. Worked with customers to correlate topology synthesis estimation results with physical design backend.Architected and developed the infrastructure to support communication between Network-on-Chip design and Cache-Coherency design tools, in Javascript, using JSON-RPC. This infrastructure has remained reliable and robust across many versions and variations of the two tools.Architected and implemented the user-to-hardware transformation algorithm that takes the Cache Coherent interconnect design intent and applies it to a verilog-based hardware generation flow.Designed and implemented a software model for clock and reset design capture for complex on-chip interconnects.
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ArchitectChip Path Design Systems Jan 2008 - Sep 2014Architected & developed a physical-design based static timing analysis tool. Features included RTL processing, timing, placement, and power calculations, and allowed users to get design feedback from inception through layout. The tool accepted Verilog, Liberty, Lef, Saif and SDC files, and emitted Def or Verilog netlists, with Power and timing results as text, JSON, or as an SQL database.Created a program to compute optimum transport delay for a given process node, and developed a virtual buffering table to ascertain feasibility for physical design with a set of constraints.Created an SQL schema and Django access routines to allow static timing path information written out as JSON to be stored and displayed in the Chip Path web portal.
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Senior Software ArchitectSilicon Navigator Jan 2004 - Jan 2008UsDeveloped a C++ API to a standalone static timing engine, abstracting out the engines internal structures while allowing static timing capabilities to be linked and called by other applications.Integrated the Concept schematic system onto Open Access (OA), allowing OA schematics to be displayed off the module hierarchy.Created an application which could read in either RTL or gate level Verilog netlist and create a hierarchical or flat OA database. -
Software ArchitectIntime Software Apr 1999 - Jan 2004Primary developer and architect of RTL timing methodology and design flow. This involved turning work-function delay information placement specific timing models, which were then used to determine RTL critical paths before RTL synthesis.Drove correlation between RTL and gate level timing from synthesis and the First Encounter tool.Developed custom wire load models and virtual buffer tree tables to allow RTL floorplans to see parasitic information which would correlate with post synthesis parasitics. -
Senior Manager EngineeringCadence Design Systems Mar 1997 - Mar 1999San Jose, California, UsManaged a group of six local and five remote developers to support CDC, TLF and SPF functions inside of Cadence, as stand-alone tools and integrated services for other products.Integrated in TLF support into Fasnet to integrate HLD timing loop into Cadence environment -
Principal Software ArchitectHigh Level Design Systems Feb 1992 - Feb 1997Project lead for the Fasnet timing system, including an RC delay calculator, RC network reducer, RC extractor, SDF path tracer, Liberty reader, Pdef interface, and custom wire load model generator. -
Member Of The Technical StaffIntel Corporation Jun 1990 - Feb 1992Santa Clara, California, UsArchitected Intel’s Physical Design Tools integration onto Mentor, Valid, and Cadence frameworks
Eric Howard Skills
Eric Howard Education Details
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University Of California, BerkeleyElectrical Engineering And Computer Science
Frequently Asked Questions about Eric Howard
What company does Eric Howard work for?
Eric Howard works for Arteris
What is Eric Howard's role at the current company?
Eric Howard's current role is Principle Product Architect and Senior Director Engineering.
What is Eric Howard's email address?
Eric Howard's email address is er****@****ris.com
What schools did Eric Howard attend?
Eric Howard attended University Of California, Berkeley.
What skills is Eric Howard known for?
Eric Howard has skills like Soc, Asic, Strategic Insights, Schema, Debugging, Eda, Static Timing Analysis, Floorplanning, Javascript, C++, Python, Logic Synthesis.
Who are Eric Howard's colleagues?
Eric Howard's colleagues are Antoine Bernstein, Chris S., Brian Huang, Sumie Aoki, Harris (Hyungsoo) Byun, Vania Melo, Zhi Qin.
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