Eric Howard Email & Phone Number

Santa Clara, Ca, Us

Campbell, Ca, Us

Campbell, Ca, Us

Campbell, Ca, Us

Campbell, Ca, Us

Implemented a streamlined SDC constraint generator for a cache coherent network on chip design tool. Created a regression environment to automatically do code coverage and launch regression tests on a compute grid.Implemented physical synthesis support for Network-on-Chip topology synthesis. Enhanced linear solver implementation to determine SOC interconnect pipeline stage insertion points. Worked with customers to correlate topology synthesis estimation results with physical design backend.Architected and developed the infrastructure to support communication between Network-on-Chip design and Cache-Coherency design tools, in Javascript, using JSON-RPC. This infrastructure has remained reliable and robust across many versions and variations of the two tools.Architected and implemented the user-to-hardware transformation algorithm that takes the Cache Coherent interconnect design intent and applies it to a verilog-based hardware generation flow.Designed and implemented a software model for clock and reset design capture for complex on-chip interconnects.

Architected & developed a physical-design based static timing analysis tool. Features included RTL processing, timing, placement, and power calculations, and allowed users to get design feedback from inception through layout. The tool accepted Verilog, Liberty, Lef, Saif and SDC files, and emitted Def or Verilog netlists, with Power and timing results as text, JSON, or as an SQL database.Created a program to compute optimum transport delay for a given process node, and developed a virtual buffering table to ascertain feasibility for physical design with a set of constraints.Created an SQL schema and Django access routines to allow static timing path information written out as JSON to be stored and displayed in the Chip Path web portal.

Us

Developed a C++ API to a standalone static timing engine, abstracting out the engines internal structures while allowing static timing capabilities to be linked and called by other applications.Integrated the Concept schematic system onto Open Access (OA), allowing OA schematics to be displayed off the module hierarchy.Created an application which could read in either RTL or gate level Verilog netlist and create a hierarchical or flat OA database.

Primary developer and architect of RTL timing methodology and design flow. This involved turning work-function delay information placement specific timing models, which were then used to determine RTL critical paths before RTL synthesis.Drove correlation between RTL and gate level timing from synthesis and the First Encounter tool.Developed custom wire load models and virtual buffer tree tables to allow RTL floorplans to see parasitic information which would correlate with post synthesis parasitics.

San Jose, California, Us

Managed a group of six local and five remote developers to support CDC, TLF and SPF functions inside of Cadence, as stand-alone tools and integrated services for other products.Integrated in TLF support into Fasnet to integrate HLD timing loop into Cadence environment

Project lead for the Fasnet timing system, including an RC delay calculator, RC network reducer, RC extractor, SDF path tracer, Liberty reader, Pdef interface, and custom wire load model generator.

Santa Clara, California, Us

Architected Intel’s Physical Design Tools integration onto Mentor, Valid, and Cadence frameworks