Eric Kong Email & Phone Number

Shanghai City, China

65/55nm DDR IO(DDR2, DDR3,LPDDR2,LPDDR3,DDR3L) library design,include calibration cell. schematic design, .v .lib generation, SI analysis, test debug. 40nm DDR IO (DDR2,DDR3,LPDDR2,LPDDR3,DDR3L) library design. schematic design, .v .lib generation, SI analysis, test debug. 28nm DDR IO (DDR3,LPDDR2,LPDDR3,DDR3L,DDR4) library design. schematic design,include calibration cell, DCC and so on. .v .lib generation. 28nm lvds schematic design. Other IO design.

Shanghai City, China

13/11 DDR2 IO schematic design。 65/55 DDR2 IO schematic design。 65 GPIO schematic design。 65 Oscillator design。 65/55 multiDDR（LPDDR，DDR2，LPDDR2，DDR3，DDR3L）IO design。 28 USB11 schematic design。 28 USB20 part schematic design。

Shanghai City, China

SRAM fail research0.13um USB2.0 part designsignal integrity research

Master'S Degree, Electrical And Electronics Engineering

integrated circuit

Bachelor'S Degree, Electrical And Electronics Engineering

microwave