Eric P. Olson Email & Phone Number

Hillsboro, Or, Us

Hillsboro, Or, Us

Hillsboro, Oregon, United States

Tampere, Finland

Design Verification flow owner for 5G SoC

Northern California

Technical Leader. Developed ASIC/SoC tools and methodologies focused on designer productivity, design reuse, automated code generation, verification, synthesis, and debug/test. -- Integral part of the development of 35+ ASICs-- Actively worked with designers to enhance productivity through improved methodologies and custom tools: IP reuse, memory wrappers, register automation, rtl code generators, scan/BIST/debug insertion, and regression/release tools.-- created a DevOps flow for automated version releasing, code & control file generation, testing, and delivering design data to DV, formal, & synthesis teams. Design reuse methodology retargeted IP and common block code to different ASICs and vendor technologies. -- Wrote verilog code generation tools for automated stitching and declaration inference, top-level connection/repeater insertion, embedded procedural code, and templates for a rich IP reuse catalog.-- Vendor independent memory/cam wrappers to allow immediate retargeting to new processes, including memory controller, process specific optimized ecc, latency matching, and bypass insertion as needed.-- Wrote verilog trace code tools (e.g. trace memory errors (from the lab) though verilog memory controller, across chip, through ecc, and memory tiling to the actual physical location).-- Developed tools for Cisco-wide board flow to enable automatic constraint generation.-- Supported and coordinated geographically remote and culturally diverse teams.

Silicon Valley

Member of the founding team. Developed ASIC tools and methodologies focused on designer productivity, design reuse, automated code generaton, synthesis, and verification. (acquired by Cisco System in 2000)

Silicon Valley

ASIC design tools developer. Wrote and enhanced a variety of programs to support the development of the full-custom MIPS R10000 and R12000 microprocessors. This included an in-house latch-based static-timing verifier and a set of programs to perform spice-based circuit checks on the schematic database, as well as verifies that specific circuits were being modeled correctly.

Phd, Computer Science

Activities and Societies: Eastman Kodak Fellowship (3 year tuition/stipend) 1st place AMD Robotic Wrestling design competition, Goshin.

Master Of Science - Ms, Electrical Engineering

Advisor: Larry Jones Thesis: incremental VLSI layout extraction